"nuclear"
Today's FPGA designs are so large and functionally complex that it is impractical to start every part of the design from scratch. One solution is to reuse the existing functional modules for the more common parts, and spend the main time and resources on those brand new and unique parts in the design. It's like when you develop an application, you don't have to directly write the code that drives the physical hardware, but just call the API provided by Windows. We call this functional module IP core (Intelligent Property).
nuclear
The core (CORE) is the core of a digital system, responsible for memory scheduling, interrupt management, arithmetic and logic operations, etc. of the entire system. Like the brain of the entire system, it is the key to realize the logic function by physical electricity. Although complex, it cannot be ignored that the core, like other digital devices, is also a typical logic device (sequential logic to be precise), and is also composed of logic gates and flip-flops, so it can be described by a hardware description language .
Since the core can be described by HDL, for each specific function and performance (that is, logic timing and function specific) core, there must be a set of HDL descriptions equivalent to it, and specific device signals, packages, etc., only It is just a physical realization of this group of HDLs that depends on specific processes. Therefore, we should realize that the so-called core is essentially a kind of intellectual property rights and a specific descriptive logical structure.
IP core
IP core is the general term for integrated circuit cores with intellectual property rights. It is a macro module with specific functions that has been repeatedly verified. It has nothing to do with the chip manufacturing process and can be transplanted into different semiconductor processes. At the SOC stage, IP core design has become an important task for ASIC circuit design companies and FPGA providers, and it is also a manifestation of their strength. For FPGA development software, the richer the IP cores it provides, the more convenient the user's design, and the higher its market occupancy rate. Currently, IP cores have become the basic unit of system design and are exchanged, transferred, and sold as independent design outcomes.
Classification of nuclei
From the way of providing IP core, it is usually divided into three categories: soft core, solid core and hard core. From the perspective of the cost of completing the IP core, the hard core is the most expensive; from the perspective of flexibility, the reusability of the soft core is the highest. Compared with the soft-core implementation, the hard-core can reduce power consumption by 5 to 10 times and save nearly 90% of logic resources.
soft core
Soft core (Soft IP Core): In the field of EDA design, soft core refers to the register transfer level (RTL) model before synthesis; specifically, in FPGA design, it refers to the hardware language description of the circuit, including logic description, netlist and help documentation etc. The soft core only undergoes functional simulation and needs to be synthesized and placed and routed before it can be used. Its advantages are high flexibility, strong portability, and allows users to configure themselves; the disadvantage is that the predictability of modules is low, and there is a possibility of errors in subsequent designs, which has certain design risks. Soft core is the most widely used form of IP core.
solid core
Firm IP Core: In the field of EDA design, a solid core refers to a netlist with plane planning information; specifically, in FPGA design, it can be regarded as a soft core with layout planning, usually with RTL code and corresponding specific process A mixed form of netlist is provided. Combine the RTL description with the specific standard cell library for comprehensive optimization design to form a gate-level netlist, which can then be used through layout and routing tools. Compared with the soft core, the design flexibility of the solid core is slightly lower, but the reliability is greatly improved. At present, solid core is also one of the mainstream forms of IP core.
hardcore
Hard IP Core: In the field of EDA design, hard core refers to the verified design layout; specifically in FPGA design, it refers to the design with fixed layout and process, verified front-end and back-end, and designers cannot modify it. There are two reasons why it cannot be modified: first, the system design has very strict timing requirements for each module, and it is not allowed to disturb the existing physical layout; second, it is the requirement to protect intellectual property rights, and designers are not allowed to make any changes to it. The feature that the IP hard core does not allow modification makes it difficult to reuse, so it can only be used for some specific applications, and the scope of use is narrow.
Advantages and disadvantages of soft core and hard core
Process Technology Independence
The soft core is built with general logic resources (LUT+FF) of FPGA. From the perspective of users, there is no difference in development difficulty between the two; in terms of performance, the speed of hard cores is generally higher than that of soft cores, and the overall power consumption is also lower.
The hard core is a special hardware circuit solidified inside the FPGA. To understand it simply, the hard core can be regarded as an ASIC embedded in the FPGA. Such as embedded RAM, embedded multiplier, PLL, etc.
One of the advantages of soft cores is process technology independence. High-level Verilog or VHDL programs do not need to use a specific process technology or standard cell library (cell library). This means that the same set of IP cores can be used repeatedly in multiple designs, or in future new generation designs. (Some soft-core IP suppliers have developed process-specific solutions that make their cores independent of process technology, but the advantages of this model are not yet clear).
Hard cores, on the other hand, are quite process technology specific. In fact, if the manufacturer changes its process parameters or cell library factors, the hard core may not work properly. Because the IP supplier has to re-test the hard core after the process parameters are changed, this feature leads to application risks.
Hard cores can be migrated to new process technologies, but considerable effort and cost must be invested in re-optimization. For some advanced microprocessor cores, it takes two years or more. Therefore, the size of the hard core is usually scaled down for the new process. This approach is simple and fast, but may reduce the benefit of the R&D team's optimal customization of the initial process.
In fact, the soft core may be designed based on a single process technology and cell library, and the design itself has nothing to do with this technology. For process technologies and cell libraries that provide the best performance, similar technologies may achieve near-optimum results, but technologies with large differences (such as with slower RAM) may not achieve the same results. This phenomenon is not absolutely critical, so soft cores are more flexible in optimization than hard cores that are scaled optically.
Customized flexibility
Another advantage that soft cores have over hard cores is that they are customized at the time of compilation, and many design options can be selected by themselves before construction.
Cache size is a common customization item at compile time. Soft-core processors allow users to choose the amount of cache memory required for their particular embedded system. The hard core cannot carry out this kind of customized setting.
Another customized design that many soft cores have is to define their own instruction set, that is, to support the function of specific instructions by themselves. For example, if the SOC has special needs, an external coprocessor can be used. Some systems may need to use instruction codes with compression functions. However, if the system does not need these functions, these redundant hardware can be removed from the soft core to save chips. area and power consumption.
The soft core also has some configuration parameters. These special customized parameters can further integrate the soft core into the design environment carried out by the SOC team. For example, microprocessor cores are often implemented using logic gate frequency circuits, but this frequency may not be compatible with some frequency routing tools. If the processor core provides a compile-time setting function, which can change the frequency of all logic gates into equivalent recirculation MUX (multi-tasking) components, the difficulties encountered in the construction process can be reduced.
Ease of Integration
Unless the hard core is built by an in-house R&D group, the soft core is usually easier to integrate into the workflow. The reason for this is that the R&D team will incorporate various RTL blocks around the licensed IP core. At this time, the core is just like other modules in the SOC, and can also adopt the same construction process.
The hard core is more like a black-box RAM component (black-box RAM), especially the core built with full customization technology. This means that hard-core suppliers must provide more black-box core models so that SoC developers can design their modules for these processors. The application difficulty of this process is originally higher than that of soft core. For example, a fully customized hard core may not have a gate-level netlist. This is because the design work is done at the transistor level and logic gates are not involved. However, the design team may need to do a logic gate-level functional simulation test with a back-annotated timing mechanism. At this time, it is difficult to perform such simulation without a logic gate-level circuit diagram.
The soft core is usually provided in a synthesizable HDL, so it has high flexibility and has nothing to do with the specific implementation process. Its main disadvantage is the lack of predictability of timing, area and power consumption. Since the soft core is provided in the form of source code, although the source code can be encrypted, its intellectual property protection cannot be ignored. The hard core is provided in the form of a fully placed and routed netlist, which is both predictable and can be optimized for power and size for a specific process or buyer. Although hard cores are less portable due to lack of flexibility, IP protection is easier to implement because there is no need to provide register transfer level (RTL) files.
The fixed core is a compromise between soft core and hard core. Most IP cores applied to FPGAs are soft cores, which help users adjust parameters and enhance reusability. Soft cores are usually provided in encrypted form so that the actual RTL is invisible to the user but flexible in placement and routing. In these encrypted soft cores, if the core is parameterized, the user can easily operate the parameters through header files or a graphical user interface (GUI). For those cores with strict timing requirements (such as PCI interface core), specific signals can be pre-wired or specific routing resources can be allocated to meet timing requirements. These cores can be classified as solid cores, and since the core is a pre-designed code module, this has the potential to affect the overall design containing the core. Since the core's setup, hold times, and handshake signals may be fixed, other circuits must be designed to properly interface with the core. If the core has a fixed layout or a partially fixed layout, this will also affect the layout of other circuits.