APB1 Peripheral Clock Enable Register (RCC_APB1ENR) Low-speed APB enable, the maximum allowable frequency is 36MHz
APB2 Peripheral Clock Enable Register (RCC_APB2ENR) High-speed APB enable, the maximum allowable frequency is 72MHz
The peripherals here are relative to the core of Cortex M3. These two registers are 32 and occupy four bytes. These two registers are located in the structure RCC_TypeDef, named APB1ENR and APB2ENR. When operating, it is RCC->APB1ENR=xxxxxxxx.
The available bits of the APB1 peripheral clock enable register are 20 bits, these are R/W, and the corresponding "peripheral" clocks are:
(1) DAC interface clock enable
(2) Interface clock enable
(3) Backup interface clock enable
(4, 5) Can 2 and Can1 interface clock enable
(6, 7) IIC2 and IIC1 interface clock enable
(8, 9, 10, 11) USART 5, USART4, USART3, USART2 interface clock enable
(12, 13) SPI3 and SPI2 interface clock enable
(14) Window watchdog clock enable, (15-20) -7 clock enable
It can be seen that one bit corresponds to one "peripheral device", 0 is off, and 1 is on.
The APB2 peripheral clock enable register is also different from the above 1. It has only 11 valid bits, and the rest of the bits are reserved (the reserved bits are read as 0). The open bits are all R/W (readable and programmable) written). The corresponding "peripheral" clocks are: (1) USART1 interface clock enable
(2) SPI1 interface clock enable
(3) Timer 1 clock enable
(4, 5) ADC2 and ADC1 interface clock enable
(6-10) Port AE clock enable
(11) Auxiliary function IO clock enable.
It can be seen that one bit corresponds to one peripheral, 1 is on and 0 is off.