1. Fill in the blanks
1. If A=+63, Y=-107, expressed in 8-bit binary, then [A+B] complement=()B, [AB] complement=()B.
A+B=-44, where 44=101100B, the original code of -44 is 10101100B, the inverse code is 11010011B, and the complement code is 11010100B
AB=170=10101010B, because it is a positive number, the original code=inverse code=complement code=10101010B
Answer: 11010100; 10101010
2. It is known that a certain data block consists of 100 bytes and is continuously stored in the memory. The logical address of the first byte is 2000H:2537H, then the physical address of the first byte of the data block is PA=()H, the base address of the last byte segment is ()H, and the offset address of the last byte is ()H.
PA=2000H*10H+2537H=22537H
The segment base address is unchanged, because it is in one segment
The first address is at number 0, the last address is at number 99, and the difference is 99 decimals. 99=63H, so the last byte offset address=2537H+63H=259AH
Answer: 22537; 2000; 259A
3. Set SS=3000H, SP=1200H, after executing the instruction PUSHF, the physical address of the top of the stack is ().
PUSHF pushes the contents of the FLAGS (16-bit) register into the SS stack register. SS points to the bottom of the stack and SP points to the top of the stack. The PUSH operation will store the high byte in the SP-1 unit and the low byte in the SP- 2 units. Therefore, the top of the stack is at SP-2, that is, 1200H-2H=11FEH, and the physical address is SS*19H+SP=311FEH.
Answer: 311FEH
4. When 8086CPU executes the instruction INT 21H, its interrupt vector is taken from the () unit of the interrupt vector table.
The interrupt type number is 21H, then the start position in the interrupt vector table is 21H*4=84H, and the end position is 21H*4+3=87H.
Answer: 84H～87H
5. The capacity of a semiconductor memory chip is 4K*8, then the address coding of any memory cell in the chip requires () bit binary number.
A capacity of 4K*8 means that there are 4K memory units and 4K memory address codes, and 4K=2^2*2^10=2^12, that is, 12-bit binary numbers are required.
Answer: 12
6. The reset signal of 8086CPU is a control signal whose symbol is RESET, which is effective at high level. After reset, 8086CPU is in the initialization state. At this time, the physical address of CS:IP is ()H, all its registers are (), and the instruction queue ().
After RESET, except CS=FFFFH, all others are 0000H. So the physical address of CS:IP is FFFFH*10H+0000H=FFFF0H.
Answer: FFFF0H; clear; clear
7. Set 8253 counter 1 to work in mode 0, counting in binary mode, with an initial value of 16 bits. When the 8253 chip is initialized, its control word bit ().
Answer: 01110000B
8. Write four instructions () that can clear AX.
： ： MOV AX ， 0 AND AX ， 0 SUB AX ， AX XOR AX ， AX
9. The PUSH AX stack instruction is () addressing mode, the source operand of MOV AX, ES:[BX] transfer instruction is () addressing mode, and the destination operand is () addressing mode.
Answer: fixed (I don’t know very well); register indirect; register
10. Execute the following program segments:
MOV AX，08701H
MOV BX，3589H
XOR AX，BX
OR BX，AXAfter: AX=(), BX=().
AX =1000 0111 0000 0001
BX =0011 0101 1000 1001 After XOR operation
AX =1011 0010 1000 1000=B288H At this time BX remains unchanged
BX =0011 0101 1000 1001 after OR operation
BX =1011 0111 1000 1001=B789H
Answer: B288H; B789H
Two, short answer questions
1. What is timing? There are three levels of description bus operation microprocessor timing: instruction cycle, bus cycle, and clock cycle. Please describe their respective definitions and the specific relationship between them in forming the CPU timing.
Answer: Timing refers to the change of signal high and low level (valid or invalid) and the time sequence relationship between them.
The instruction cycle refers to the process from fetching, decoding, reading and writing operands to completion of an instruction. Several bus cycles form a command cycle.
Bus cycle refers to the process of data exchange between CPU and external (memory or I/O port) through bus operation.
The clock cycle is the time reference of the CPU and is determined by the main frequency of the computer. For example, the main frequency of 8086 is 5MHz, the clock cycle is 200ns, and the basic bus cycle of 8088 requires 4 clock cycles.
2. If the data segment is defined as follows:
DATA SEGMENT AT 1000H
ORG 0100H
DATA1 DB 10H,52H,3 DUP(02H)
DATA2 DW 1122H,2 DUP(?)
DATA3 DD 5*20H,0FFEEH
DATA4 DB 'HELLO'
DATA ENDSThe ASCII of the "A" character is 41H. Try to draw a schematic diagram of the storage of the DATA segment.
Answer: DATA1 (byte type) DATA2 (word type) DATA3 (double word type) DATA4 (word type)
1000H:0100H 10H 1000H:0101H 52H 1000H:0102H 02H 1000H:0103H 02H 1000H:0104H 02H
1000H:0105H 22h 1000H:0106H 11am 1000H:0107H ? 1000H:0108H ? 1000H:0109H ? 1000H:010AH ?
1000H:010BH A0H 1000H:010CH 00H 1000H:010DH 00H 1000H:010EH 00H 1000H:010FH EEH 1000H:0110H FFH 1000H:0111H 00H 1000H:0112H 00H
1000H:0113H 48H 1000H:0114H 45H 1000H:0115H 4ch 1000H:0116H 4ch 1000H:0117H 4FH
3. The data defined in the data section of the program is as follows:
DATA SEGMENT
VAR DB 'STRING'
DB 10
DB 'CODE'
DB 50
DATA ENDSPlease indicate whether the following instructions are correct? why?
（1） MOV AX ， VAR + 5
（2）MOV BX,4*3
MOV SI, 4
MOV AX, VAR [BX] [SI]
（3）MOV BX,6
MOV SI, 3 + 2
MOV AX, OFFSET VAR [BX] [SI]
INC [BX]
Answer: The structure of var is like this
S T R I N G AH C O D E 32h (1) Error. VAR is byte type, AX is word type, so the type does not match
(2) Error. The first two instruction pairs, BX=CH, SI=4H, VAR is byte type, and does not match AX type
(3) Error. The first two instructions are correct, BX=6H, SI=5H, the latter two are incorrect (I don’t know why)