Chip design: OTP

foreword

We have also learned OTP before, but the dimension of standing is relatively high, and the wrong angle should be the angle. We look at it from the user's point of view.

Today we look at the design of OTP from the perspective of chip designers.

The learning content comes from the predecessors: https://zhuanlan.zhihu.com/p/404680588

1. Overview of OTP

• MTP: Multiple-Time Programmable, can be programmed multiple times

• FTP: Few-Time Programmable, the number of programmable times is limited

• OTP: One-Time Programmable, only allows programming once, once programmed, the data is permanently valid

OTP (one time programmable) devices, that is, one-time programmable devices, belong to non-volatile memory. Compared with multiple-time programmable devices such as MTP and Flash, the programming process is irreversible, and it is suitable for fixed programs. changing applications.

Because its cost is lower than multi-time programmable devices, it is suitable for use in electronic products with certain flexibility, low cost and performance that need to be refreshed, such as power management chips [1].

The power management chip is mainly based on analog circuits. Due to the influence of process manufacturing errors, the chip that comes back from the tape often needs to be calibrated for parameters. By adding OTP and registers to the chip, the determined value will be programmed into the OTP after debugging . After the chip is powered on, the OTP value is loaded into the register, and the analog circuit parameters are calibrated.

Figure 1 is a block diagram of a common analog chip circuit system. After the chip is powered on, the OTP value is loaded into the register to complete the parameter calibration of the analog circuit, and the low-speed interface IP (usually I2C/SPI/UART, etc.) is embedded to facilitate OTP, The reading and writing of registers greatly improves the convenience of debugging.

OTP is usually provided by IP manufacturers. This article takes the TSMC0.18um BCD process OTP provided by EMEMORY as an example, and summarizes the information and precautions that OTP read and write control needs to pay attention to from the perspective of a digital designer.

2. OTP interface

The data sheet of OTP records its capacity, IP area, process details, electrical characteristics, etc. in detail. These parameters can be known by consulting the data sheet and will not be explained here. The first thing to pay attention to is the pin information of OTP, as shown in Figure 2.

• PA: address line

• PDIN: write data line

• PDOB: OTP read data line

• PTM: The test mode is enabled, and the values ​​are different in different working modes

• PWE/PPROG: OTP programming control pin

• PRD: OTP read control pin

• VSS/VDD/VPP: Power related pins

3. OTP timing

3.1, OTP power-on sequence

Figure 3 is the power-on timing diagram of OTP, VSS is the ground of OTP, and the VDD power supply pin is the Power supply of OTP, which must be connected as long as OTP works. VPP is the high-voltage power supply pin of OTP, which is generally required when OTP programming Immerse high voltage, and leave open or the same voltage as VDD when OTP is read.

Although the parameters of Tvds and Tvdr in most OTP data sheets are marked as 0, when we design the control circuit, we still design according to the power-on sequence shown in the figure. In the impression, in the design of a certain project, VDD and VPP are designed to be at the same time Power-off, although there is no problem in the actual application of both power-off at the same time, but the model still reports a warning during simulation, so it is recommended to strictly follow the power-on sequence diagram for logic design.

Trst (Control Signal Enable Time) is an important timing parameter (min=20ns), which indicates the minimum time that the OTP pin signal needs to wait after the VDD signal is stable.

3.2. OTP controls the timing of PIN and PTM

Tms and Tmh in Figure 4 refer to PTM Mode Setup Time and PTM Mode Hold Time respectively, which represent the minimum time for PTM to remain stable before the rising edge of Control Pins and the minimum time for PTM to remain stable after the falling edge of Control Pins.

Control Pins refer to PRD, PPROG, PWE. It is worth mentioning that OTP usually runs in user mode, reading data or programming. In both cases, the value of PTM is 2'b00, so the value of PTM generally remains constant after power-on. Special attention should be paid to this point if there are situations where the value of PTM changes in your design.

3.3, OTP user mode read data timing

From the timing in Figure 5, an approximate flow of OTP reading data can be sorted out:

• 1. Power up VPP, 5V

• 2. Power on VDD, 5V

• 3. Prepare the address data PA

• 4. Pull up PRD and wait for PDOB data output

• 5. Pull down PRD

• 6. Turn off VDD

• 7. Close VPP

The above is just a rough rough flow. The specific design needs to be considered in conjunction with the clock in the project. All the timing parameters marked in Figure 5 must be considered in the design.

3.4, OTP user mode write data timing

According to Figure 6, it can be seen that the framework of writing OTP data flow is similar to that of reading data. They all turn on the power signal in order, and then give the control signal Note that two voltage domain signals are required to write OTP data . First, turn on the VPP pin 5V Enable, then turn on the VDD pin 5V to enable, and finally turn on VPP7.5V to enable;

When shutting down, first turn off the VPP7.5V enable (note that the voltage of the VPP pin is 5V at this time), then turn off the VDD 5V enable, and finally turn off the VPP 5V enable.

4. OTP digital-analog interface design

• SCLK: clock interface, the clock signal of the ASIC chip is provided by the analog circuit.

• POWOK: The analog gives a signal that the clock and power supply of the digital part are stable, and it needs to be confirmed with the analog engineer, such as whether the power supply and clock of the digital module are stable when the signal is "1", and if it is unstable, do you need to do debounce (delay) ), usually this signal is connected to the top layer of the asynchronous reset of the digital circuit.

• OTPVPP/OTPVDD: VPP and VDD power interface pins of the OTP IP module

• OTPVDDEN: OTP VDD power enable signal

• VPP5EN: OTP VPP power supply low voltage (5V) enable signal

• VPP7P5EN: OTP VPP power supply high voltage (7.5V) enable signal

• REGS_XX: Register configuration information, used for analog circuit parameter calibration

• SDA/SCL: Low-speed interface IP PAD signal (such as I2C)

Note: OTPVDDEN, VPP5EN and VPP7P5EN are the power enable signals from the digital circuit to the analog circuit . After the digital circuit gives a valid power enable signal, the analog circuit may need a response time, so this response time should be confirmed with the analog engineer. Only when the OTP Other control signals can only be given after the power supply signal is stable .

5. OTP simulation model

The P manufacturer will provide the .v model file for the simulation of OTP read and write. In the OTP model, OTPVPP is 1 for high voltage (7.5V), OTPVPP for 0 for normal voltage (5V), and OTPVDD for "1" for normal voltage. Voltage (5V). Therefore, when using the model simulation, turning off the power supply should be represented by a high-impedance state.

wire OTPVDD = OTPVDDEN ? 1’b1 ：1’bz
wire OTPVPP = VPP7P5EN ? 1’b1 ：(VPP5EN ? 1’b0 ：1’bz)

OTP can only be programmed once, and an otp.dat file will be loaded when the OTP model is used for simulation. The format is as follows:

@00000000 ff
   @00000001 ff
   @00000002 ff
   @00000003 ff

The one after @ indicates the address, and ff indicates the data of otp. The value read by default in the OTP example in this article is the bitwise inversion of the value in the otp.dat file.

For example, @00000000 ff means that the data read from the OTP0 address is 00000000, and @00000001 fe means that the data read from the OTP1 address is 00000001. During simulation, if you manually modify the value of otp.dat (change "1" to " 0") indicates that the bit corresponding to the OTP has been modified.

6. OTP common function design

6.1, OTP automatically loads data after power-on

Since OTP often assists analog circuits in trimming , it is necessary to have an OTP power-on automatic loading function (the OTP address is loaded according to 0, 1, 2, 3...) , pay attention to the data read out of the OTP mentioned in this article when it is not programmed All are 0, so the value of the register should be the bitwise XOR of its initial value and the OTP mapping address value:

assign regs_0x01 = auto_load ? 8’h02^otp_wdata:bus_wdata

The initial value of the register regs_0x01 is 8'h02, otp_wdata indicates that the data comes from OTP, and bus_wdata indicates that the data comes from the low-speed interface. The exclusive OR logic can ensure that the initial value of the register will not be overwritten when the OTP is not programmed. You need to pay attention to programming to the value you want The influence of the initial value of the register and the bitwise XOR of the OTP data should be considered.

For example, the initial value of regs_0x01 is 0000_0010, and if you want to change it to 0000_0001, then the readout value of OTP is 0000_0011, then you need to program all [1:0] of the OTP address.

6.2, OTP register operation design

The OTP automatically loads data when it is powered on. The read address and control signal are generated by the hardware. With the low-speed interface IP, the OTP can be read and written through the low-speed interface, and the debugging will become flexible.

As shown in the following 4 tables, the OTP operation register SPEC is defined. Through the operation of the register, the operation of the OTP is completed indirectly. One thing to note is that the address, data and control signals of the OTP sent through the low-speed interface should also meet the requirements of the OTP. Timing requirements, if the low-speed interface rate is too slow, it may not be suitable to use software to operate OTP.

Commonly used low-speed interfaces such as I2C, as a slave can support 100K/400K bit/s, which can meet the timing requirements of common OTP.

6.3, OTP page design

Considering the flexibility of the application, it is sometimes necessary to paginate the OTP. **For example, an OTP with a size of 8X8bit is divided into two pages, and it is required to be able to choose to load data from addresses 1, 2, 3 or 5, 6, and 7.

The usual practice is to use the otp data at address 0 as a judgment bit. As shown in Table 7, the OTP is not programmed, and the value of PAGE_SEL is 00. At this time, the data of OTP1~3 is loaded. If you want to load the data of OTP5~7, program the OTP address 0 data [1:0] as 11.

The implementation method is also very simple, still taking 8X8bit as an example, there is the following code

assign pa = auto_load_flag ? {otp_page_add,auto_load_addr}:reg_otp_pa;

auto_load_addr is the accumulative address when otp automatically loads data,

First, the data at address 0 is loaded, and after the loading is completed, the value of otp_page_add is judged by combinational logic.

If it is 0, the subsequent address is 1, 2, 3,
if the value of otp_page_add is 1, the subsequent address is 5, 6, 7.

6.4, OTP power isolation design

We know that in CMOS digital logic circuits, when a certain signal is VDD, we consider it to be logic 1, and if it is GND, we consider it to be logic 0. But when a certain circuit is not powered, its output will lose its drive . If the output network is not driven by other signals, its level will be in a high-impedance state . In other words, the voltage is unknown [3].

Therefore, if the power supply of the OTP module is cut off, the output of the OTP will have an indefinite value . Therefore, it is necessary to add an Isolation Cell between the output of the OTP and the module connected to it . When the power is turned off, the OTP The output of the OTP is fixed at a certain level, and after the power is turned on, the output of the OTP is equal to the input to ensure correct data output.

For the output data isolation of OTP, the AND gate can be used, and the AND gate logic of the standard cell library can be directly called to connect.

The sample code is as follows:

AND2X1TAS10 isolation_cell_and2_datao7 (.I1(pdob[7]), .I2(otpvdden), .O(otp_dout[7]))；
AND2X1TAS10 isolation_cell_and2_datao6 (.I1(pdob[6]), .I2(otpvdden), .O(otp_dout[6]))；
AND2X1TAS10 isolation_cell_and2_datao5 (.I1(pdob[5]), .I2(otpvdden), .O(otp_dout[5]))；
AND2X1TAS10 isolation_cell_and2_datao4 (.I1(pdob[4]), .I2(otpvdden), .O(otp_dout[4]))；
AND2X1TAS10 isolation_cell_and2_datao3 (.I1(pdob[3]), .I2(otpvdden), .O(otp_dout[3]))；
AND2X1TAS10 isolation_cell_and2_datao2 (.I1(pdob[2]), .I2(otpvdden), .O(otp_dout[2]))；
AND2X1TAS10 isolation_cell_and2_datao1 (.I1(pdob[1]), .I2(otpvdden), .O(otp_dout[1]))；
AND2X1TAS10 isolation_cell_and2_datao0 (.I1(pdob[0]), .I2(otpvdden), .O(otp_dout[0]))；

pdob[7:0] is the OTP output data, otpvdden is the OTP VDD power control enable signal, and the logic of the AND gate can directly call the digital cell library for instantiation.

references

[1]. Men Mengmeng. Development of a one-time programmable memory based on CMOS technology [D]. Xidian University, 2016.

[2]. TSMC 0.18um Pure 5V BCD Process 128x8bit One Time Programmable Device Datasheet

[3]. Sun Yiqun. Low power consumption physical realization technology of digital integrated circuit and UPF

[4]. Low Power Methodology Manual For System-on-Chip Design