How to tune SiC MOSFET drivers to reduce power loss

Author: Xiou

Reference materials: ST official website application note "AN4671".

1. How to reduce conduction loss?

**Conduction loss: **All MOS tubes have conduction internal resistance after they are turned on. When the current flows, power loss will occur. Generally, RDS(ON) is used to represent the conduction loss. Generally speaking, it is proportional to the size of the MOS. Inversely proportional, the larger the volume, the smaller the on-resistance can generally be made. The calculation of the conduction loss is as follows, simply speaking, it is the product of the current flowing through the MOS tube and the voltage drop between the MOS tube DS.

SiC MOSFETs require higher gate voltage amplitudes than standard superjunction MOSFETs or IGBTs. We recommend using a gate drive with a +20 V bias to reduce RDS(on), thereby reducing conduction losses.

Therefore, SiC MOSFETs offer clear advantages over other SiC devices:

· DC Current Requirement - It does not require any gate current to maintain the on state.
· Simple drive circuit - requires only gate resistors and a simple 0 to 20 V input voltage.

Driving a SiC MOSFET with a positive bias beyond 20 V is unnecessary, or even undesirable, because the VGS absolute maximum rating is +25 V and can be as low as 18 V, but at 20 A, 25 °C , will increase RDS(on) by about 25%.

Using a negative gate bias keeps the device completely off to minimize switching losses.

2. How to reduce switching loss?

**Switching loss: **Because when the MOS tube is turned on or off, its voltage will not immediately rise to the power supply voltage or drop to OV, there is a certain slope, so there will be switching loss in this process, its calculation method as follows:

Among them, Vin represents the input voltage, lo represents the output current, tr represents the time for the output voltage to rise from OV to the power supply voltage when the MOS tube is turned on, tf represents the time for the output voltage to drop from the power supply voltage to OV when the MOS tube is turned off, and fsw Indicates the switching frequency:

SiC MOSFETs are specifically designed to be easy to drive and can operate at switching frequencies five times higher than comparable IGBTs, making designs more compact, reliable and efficient for some applications such as solar inverters, high voltage power supplies and high efficiency drives .

In order to optimize switching performance and achieve the "quantum leap" of power electronics, certain unique operating characteristics need to be understood and implemented.

The main aspects affecting switching performance are:
Turn-off energy (Eoff) depends on Rg and VGS-OFF (negative bias gate voltage)
Turn-on energy (Eon) depends on Rg
Miller effect affects Eon and Err (reverse recovery loss)
gate drive current requirements

All tests are based on VGS-on=+20V. The influence of the above parameters on switching performance can be extended to the whole family of SiC MOSFETs, the difference lies in the requirement of gate current, which is largely determined by the rated current of the device in relation to the amount of gate charge.

2.1 Turn-off loss (Eoff) depends on Rg and Vgs-off

As with any majority carrier device, SiC MOSFETs have no tail, so the turn-off loss (Eoff) depends on the overlap area between the drain-source voltage and the drain current during the voltage rise time and current fall time.

Inherent turn-off losses depend on the device itself (rather than turn-on losses, as boost converters and many other topologies rely on the reverse recovery charge of an external silicon or silicon carbide diode.), so unmatched silicon carbide The turn-off speed of the MOSFET is what characterizes this new technology and sets it apart from other 1200 V power devices.

Eoff can be lowered by drawing more current from the gate by:
Lowering the gate resistance (Rg)
Using a negatively biased gate voltage during turn-off

Eoff of SCT30N120 depends on the gate resistance as shown below.

Apparently, as the gate resistance decreases, there is a corresponding increase in drain-to-source overshoot (peak voltage over VDD), but the SCT30N120 exhibits only a slight change in overshoot. The gate resistance is varied from 1Ω to 10Ω, and the maximum VDS across the MOSFETs differs by only 50 volts. Therefore, even when Rg=1Ω, the voltage margin is at least 20%. Of course, the parasitic inductance between the drain and the positive clamp voltage should be minimized.

The waveform diagram below clearly depicts the variation of Rg with respect to voltage overshoot and Eoff.

These figures show that the turn-off losses can be significantly reduced by reducing the gate resistance during the voltage rise time. Furthermore, in order to switch the device and obtain low conductance values, a small gate charge is required:

When Rg=1Ω, the gate-source Miller plateau is eliminated (see Figure 4)
When Rg=10Ω, a VGS plateau with a period of tens of nanoseconds is obtained (see Figure 5)

Using a negative voltage to turn off the MOSFET helps to further reduce turn-off losses because it increases the voltage drop across the gate resistor, thereby drawing charge to the gate faster. For any gate resistor value, the cut-off voltage drops from 0 V to -5 V, and Eoff decreases by 35% to 40%.

During shutdown, negative voltage bias has a significant impact on power dissipation. Later, we discuss how to reduce the Miller effect.

2.2 Turn-on loss (Eon) vs. Rg

Turn-on performance can also be improved by reducing gate resistance. Compared to turn-off, the change is less pronounced, but turn-on losses are reduced by almost 40% when the gate resistance is varied in the range of 1 to 10Ω. Lower energy consumption must be compatible with di/dt related EMI specifications, since di/dt increases significantly with low Rg values.

This negative bias gate voltage has no effect on the turn-on losses of individual SiC MOSFETs and only slightly increases the effective turn-on delay time due to the larger gate voltage swing.

Negative gate drive bias can significantly improve the turn-on performance of half-bridge derived topologies (half-bridge, full-bridge, etc.) because of the Miller effect affecting Eon.

2.3 Miller effect of turn-on loss Eon and reverse recovery loss Err

When the lower MOSFET of the half-bridge is turned on, a voltage change dVDS/dt occurs across the upper MOSFET. This creates a charging current that charges the parasitic capacitance CGD of the upper MOSFET through the Miller capacitor, gate resistor and CGS (capacitors CGD and CGS form a capacitive voltage divider). If the voltage drop across the gate resistor exceeds the threshold voltage of the upper MOSFET, a parasitic turn-on known as "Miller turn-on" or "Miller effect" occurs, which can significantly affect the switching of the entire bridge arm loss. Parasitic turn-on can also occur when the high-side MOSFET turns on and current flows through the Miller capacitance of the low-side switch.

This phenomenon also occurs with SiC MOSFETs. In the test circuit below, the high-side SCT30N120 applies a negative supply voltage (Voff-HS is in the range of 0 to -10 V) at the gate and source and a series turn-off gate resistor (Roff-HS) maintains off. When the low-side switch SCT30N120 is turned on, it causes the voltage change dVDS/dt of the high-side switch. Gate resistors Roff-LS and Ron-LS are connected to the low-side MOSFET to turn off and turn on. The test circuit below shows how the Miller turn-on of the high-side MOSFET negatively affects the Eon of the low-side MOSFET.

The analysis of the Miller conduction phenomenon includes studying how the Eon of the low-side MOSFET and the ERR of the high-side MOSFET are affected by the variation of Roff-HS, Ron-LS and Voff-HS.

The reverse recovery loss Err is the switching energy dissipated after the intrinsic body diode of SiC MOSFET is turned on. In the absence of the Miller effect, it is negligible due to the excellent reverse recovery characteristics of SiC. However, in the presence of Miller conduction, the reverse recovery energy significantly affects the overall switching loss.

In a half-bridge converter, the Miller effect may occur under one or more of the following conditions:
High dv/dt (low Ron-LS)
High Roff-HS
High MOSFET intrinsic Rg
· High capacitance CGD/CGS ratio

So three combinations of Roff-HS, Ron-LS are tested while Voff-HS is increased from -10 V to 0 V:

1. Ron-LS=4.7Ω, Roff-HS=2.2Ω (best Miller effect case)
2. Ron-LS =4.7Ω, Roff-HS =15Ω (worst Miller effect case)
3. Ron-LS = Roff-HS =15Ω (middle case)
4. To maintain a safety margin relative to the -10 V VGS absolute maximum rating, negative voltages should not exceed -6 V
   (Voff-HS = -10 V is assumed for the integrity of the test results).

Therefore, when SCT30N120 works in half-bridge derivative topology, at least one of the following rules must be adopted:

1. Implement separate turn-on and turn-off paths, always maintaining the correct ratio between turn-on and turn-off gate resistors RG-ON > 1.5*RG-off.
2. Use a negative cutoff voltage in the range of -6 V to -4 V to keep the MOSFET off.
   While condition 1 is satisfied (which is easier to implement), a small negative gate-source voltage (about -2 V) can further reduce losses, although it is not required.

2.4 Requirements for driving current

The gate current required to turn the MOSFET on or off can be calculated from the gate charge, which can be read directly from the relevant data sheet.
The SCT30N120 total gate charge (Qg) is typically 106 nC at VDD=800 V, ID=20 A, VGS= -2 to 20 V.

The lower image shows the total amount of charge measured by integrating the gate current during turn-on.

Since SiC MOSFETs have the lowest figure of merit (FoM) RDS(ON)*Qg of all 1200 V switches, the driver must source and sink relatively small total gate charge during any switching cycle.

When the driver's current sourcing and sinking capabilities are insufficient, the excellent switching performance of SiC MOSFETs is compromised because, as mentioned above, switching energy is closely related to gate resistance.

For maximum switching speed, the driver must be able to source and sink peak gate current at Rg = 1Ω, VGS-on = +20V and VGS-off = -2 V (see Figure 2).

The images below during turn-on and turn-off clearly show the requirements for the driver to source and sink current when driving the SCT30N120.

In both cases, the gate peak current was slightly lower than 2A, and under other test conditions (higher device temperature and lower drain current case), the gate current was slightly lower at turn-off, and the turn-on , the gate current increases accordingly.

The voltage drop across the gate resistor and the gate current are limited by the di/dt of the parasitic source inductance and the drain current, Figure 11 shows that at turn-on, the large ringing of the gate current is caused by the oscillation of ID and the source caused by inductance.

Ideally, if we want to remove the influence of parasitic inductance, we hope that the gate supply current exceeds 2A during turn-on, and during turn-off, Rg = 1Ω (see Figure 12), the gate current should be quite stable and not affected by leakage current.