Some common problems when using power MOSFET (2)
1. Gate-source voltage transient
Excessive voltage transients can penetrate thin gate-source oxide layers and cause permanent damage. Unfortunately, such transients are generated in power switching circuits and can couple to sensitive MOSFET gate inputs. The gate drive waveform should be carefully viewed when testing to ensure there are no positive or negative transients that exceed the limits of the device (power MOSFETs are typically +/-20 V, but this should be confirmed on the data sheet).
During the on or off operation of the gate drive, high dVDS/dt occurs when the device transitions from the on state to the off state and vice versa. Considering the presence of parasitic inductances in the gate, source and drain leads, as well as the MOSFET CGD (Miller capacitance), it is understandable that the combination of these parasitic parameters can produce a transient voltage between the gate and source.
Fortunately, gate capacitance CGS can mitigate this effect.
The CGS/CGD ratio must be as high as possible to minimize drain-source voltage coupling. It is also important to optimize the PCB layout to minimize parasitic inductance.
In some cases, designers add small gate-to-source capacitance to help reduce these spikes, although this also slows down the switching speed of the MOSFET.
The CGS and CGD values are voltage dependent, so the values from the MOSFET datasheet are usually not quoted directly. It is more convenient to look at the related charge values QGD and QGS.
The charge ratio is usually expressed as: QGD/QGS or QGD/QGS(TH). Lower values mean that the device is less susceptible to induced conduction through CGD coupling
Influence.
2. Safe work area
The development of modern power MOSFETs focuses on fast switching with ultra-low RDS(on), so reducing the die area has become a development trend. Therefore, the power handling capability of a given RDS(on) device generally decreases, especially in linear mode of operation (in the saturation region).
When designing a power MOSFET (or any other type of power transistor), one must pay close attention to the SOA diagram and ensure that the device never operates outside the defined limit lines. If these limits are exceeded, reliable design is impossible!
In some applications, operation in the saturation region is continued for a period of time, such as inrush current limiting or "hot swapping." In these cases, special attention must be paid to the SOA limits of the required pulse duration to ensure that these limits are never exceeded.
In typical switching applications, SOA cannot be ignored because the device passes through the saturation region on every switching cycle except for zero-voltage or zero-current switching transitions. These transitions occur very quickly, so under specified conditions, the MOSFET can withstand higher current pulses. However, it is recommended to check whether you are working within the SOA constraints.
It is important to remember that when you slow down a MOSFET's turn-on or turn-off speed to reduce EMI or turn-off transients, the operating time in the saturation region increases.
So how is the SOA curve of the power MOSFET obtained? Can it be used as a safety standard for design?
The SOA curve of any company mainly consists of three parts: the resistance limitation area, several current and voltage straight lines limited by pulse power, and the maximum voltage straight line. The maximum voltage value is the rating in the data sheet. Several current and voltage straight lines limited by pulse power are actually calculated values based on the transient thermal resistance, on-resistance and maximum allowable junction temperature in the data sheet, and are all based on TC=25 degrees. TC represents the temperature of the exposed copper of the package. In actual applications, the temperature of TC is much higher than 25 degrees. Therefore, the SOA curve cannot be used as a design verification standard.
3. Induction conduction and breakdown
Turn-on is a phenomenon that occurs when MOSFETs are used in fast switching applications, where a high dVDS/dt transition occurs at the drain when the device is in the off state. This typically occurs in hard switching applications such as switching power supplies and motor drive inverters, where two MOSFETs are used in a half-bridge configuration.
The high-side and low-side MOSFETs alternately turn on and off, leaving a short dead time between the turn-off of one device and the turn-on of the other to prevent overlap and thus the creation of very high current pulses . When the low-side MOSFET is turned off, after the dead time has elapsed, the high-side turns on. When this occurs, the HB node quickly transitions from the zero volt state to VBUS.
The diagram above shows how "C.dv/dt" causes a current pulse to couple to the gate via CGD, with the gate voltage pulling it to the zero volt state via RG(EXT). This current pulse can cause a voltage spike at the gate. It is important to remember that the MOSFET may also have a large internal gate resistance RG(INT), so the induced gate spike that appears on the wafer may be larger than the spike observed at the gate terminal.
If the inductive spike exceeds the MOSFET VTH, the device will briefly conduct partially before the high-side MOSFET fully turns off. When both devices are partially on, high currents can flow through the half-bridge, which can exceed SOA limits and damage one or both devices.
3.1 How to avoid inductive conduction
A MOSFET with higher CGS/CGD means lower QGD/QGS and QGD/QGS(TH), making it less susceptible to drain-source voltage coupling.
For hard switching applications, a QGD/QGS of 0.5 to 0.8 and a QGD/QGS(TH) of less than 1.0 is recommended.
It should be noted that lower QGD/QGS devices may experience larger ringing at the gate, but this depends on the RG(INT) value and circuit loop inductance.
Inductive turn-on can be reduced by slowing down the switching transition speed, thus reducing dv/dt. This can be accomplished by increasing Rg_on to slow down the conduction speed of the high-side device. Depending on the circuit switching characteristics, the high-side and low-side gate drive networks may be the same or different. Reducing the conduction speed also reduces radiated EMI, but also increases switching losses, so the trade-off needs to be carefully considered.
Another way to reduce inductive turn-on is to use a "turn off faster than on" type of gate drive network, which The network includes diodes and resistors to support strong gate pull-down functionality while supporting slower turn-on. This approach works well in the off state, but also results in a fast shutdown, which tends to produce a higher drain transient voltage that has the risk of causing an avalanche - something to consider during design Another balance.
The drive circuit at the moment of turn-off can provide a path with the lowest possible impedance for the capacitance voltage between the MOSFET gate and source to quickly discharge, ensuring that the switch tube can turn off quickly. In order to quickly discharge the capacitance voltage between the gate and the source, a resistor and a diode are often connected in parallel to the driving resistor, as shown in the figure, among which D1 is commonly used as a fast recovery diode. This reduces the turn-off time and reduces the losses during turn-off. Rg2 prevents excessive current from burning the power IC during shutdown.
The third method isto add an external gate-to-source capacitor. This approach can reduce the magnitude of the inductive gate transient by increasing the effective CGS/CGD, but this slows down switching and should be applied only when necessary and kept to a minimum.