Some common problems when using power MOSFET (3)
1. Body diode
The body diode is an inherent part of the MOSFET structure and is formed by the p-n junction between the p-body layer and the n-epi layer as shown in the figure. Power MOSFETs are three-terminal devices with their body and source connected internally. This can be understood by looking at the circuit symbols for N-channel and P-channel devices.
Like other p-n junction diodes, MOSFET body diodes have minority carrier reverse recovery and therefore a certain reverse recovery time. Reverse recovery occurs when a diode is reverse biased while carrying forward current.
Reverse recovery is characterized in the data sheet by time trr and reverse recovery charge Qrr when tested under a specified set of conditions.
In interval (1), the diode is off and starts conducting in interval (2). At the end of the conduction process, the diode becomes forward biased. Reverse recovery charge accumulates and is stored, while the forward biased diode carries positive current during interval (3). At the beginning of the switch-off interval (4), the current decreases to zero and then flows in the opposite direction. Reverse recovery is completed during interval (5) and turn-off is completed during interval (6) when the diode is blocked. The shaded area in the figure represents Qrr, which is a key device parameter for hard commutation robustness.
In half-bridge power switching circuits, body diode reverse recovery becomes important when introducing high switching currents into inductive loads. Consider a synchronous buck regulator operating in continuous conduction mode (CCM), with Q1 on and Q2 off, where current IL flows from the half-bridge switch node.
When Q1 turns off, the inductor current passes through the Q2 body diode, and then Q2 turns on after the dead time. At the end of Q2's conduction (synchronous rectification) period, it switches off again, so current flows through its body diode again. At the end of the dead time, Q1 conducts and Q2 body diode recovery becomes critical. If Q1 conducts too fast, the peak reverse recovery current of Q2's integrated body diode will rise too quickly, exceeding the peak reverse recovery current rating, and the device may be damaged!
By slowing down the change rate of current during commutation, the peak reverse recovery current of the body diode can be reduced. By slowing the rise rate of the gate drive, the rate of change of the current can be controlled. Using this technique, the peak reverse recovery current can be reduced to an acceptable level at the expense of prolonged High power switching cycles, so there is always a trade-off.
For operation at frequencies up to around 20 kHz, the applied gate drive signal can be slowed down to reduce the peak
value reverse recovery current of the "paired" device body diode, This is a great practical solution. At higher frequencies, special attention must be paid to the voltage and current required for MOSFET switching and appropriate device and gate drive scheme selection.
2. Packaging and PCB layout considerations
The inductance depends on the internal geometry of the drain and source connections. Therefore, it is necessary to consider the type of package required for any design, not only in terms of its
thermal characteristics, but also in terms ofpackage inductance, which may not be clearly stated in the data sheet. In short, when switching currents are high in hard commutation, the inductance of the SMD package needs to be as low as possible and good PCB layout is required to achieve acceptable performance and avoid reliability and potential EMI issues. When designing a PCB for power applications, it is recommended to use the manufacturer's recommended device packaging and ensure that handling and soldering guidelines are followed.
Stray inductance in power switching circuits increases the amplitude and energy of overvoltage transients, making it necessary to reduce switching speed to avoid avalanche events. Electrical
voltage transients are produced by rapid changes in current:
where LS is determined by the current loop starting from the nearest bus decoupling capacitor, through the switching element, and back to the capacitor.
In the circuit board layout, the inductance of the current loop depends on the distance of the traces forming the loop and the
distance of the DC bus decoupling capacitor from the MOSFET. Longer traces and larger loop areas can also produce radiated EMI. Loops can be minimized by placing the MOSFETs close to each other and as close as possible to the DC bus decoupling capacitors. This can be accomplished by using two or more layers of traces in the PCB and placing the return current path directly beneath the current path, starting with the decoupling capacitor and passing through the MOSFET to provide tight coupling. The return path usually takes the form of a power ground plane.
This is usually accomplished by retaining one or more copper layers in a multilayer PCB. It should be mentioned here that signal/digital ground and power ground should be separated to avoid "ground bounce", which can affect sensitive control circuits.
It is best to connect the power supply and signal ground at a single point, preferably a decoupling capacitor ground connection.
3.MOS parallel connection
We often encounter the design of parallel connection of MOS tubes, and there are many problems.
For high-current power systems, it is important to understand and control the steady-state and dynamic current balance between parallel MOSFETs. When the device operates in the ohmic region, steady-state current balancing is possible because RDS(on) has a positive temperature coefficient. Current balancing can be achieved,
because if a device conducts more current because its RDS(on) is lower than its parallel counterpart, its die temperature will increase, thereby increasing its RDS (on) and thus achieves current balance.
To operate effectively, devices should be placed close together and connected to their drains and sources with traces of the same length and width.
However, under switching conditions achieving paralleling becomes more difficult, even more so as frequency increases. This is because dynamic effects come into play during each turn-on and turn-off operation, which can subject one device to more stress than others. Mismatching of the following device parameters can affect current distribution and power dissipation during switching: gate threshold (VTH), transconductance (gfs) gate-source capacitance (CGS), Miller capacitance (CGD) and body diode recovery (Qrr), and RDS(on). If the parts are not properly matched, one device may carry most of the current during switching, which may exceed the SOA limit.
Special attention should be paid to power and thermal stability limitations. In addition to this, the thermal equilibrium mechanism described earlier requires some time to reach equilibrium, which is not possible when switching rapidly. In parallel applications, the data sheet should be checked for tolerances on the above parameters, as tighter tolerance control can result in better dynamic balance.
In PCB layout, **gate return and current return inductance need to be as consistent as possible. **Circuit layout should be as symmetrical as possible to maintain current balance in parallel MOSFETs. The gates of parallel devices can be decoupled by small ferrite beads placed across the gate connections, or by a single resistor in series with each gate to prevent parasitic oscillations.
The design of the gate drive circuit is also critical. Because when the first MOSFET turns on, it is unlikely that the parallel MOSFETs will turn on or off at the same time, a rapid voltage swing occurs at the source node. This can occur through CGD coupling of slower parallel devices,and produce a voltage spike at the shared gate connection. This creates oscillations as the MOSFET turns on and off quickly, potentially damaging the MOSFET and gate driver. To prevent this, each parallel MOSFET should have its own gate drive network placed between the gate and the shared connection point of the gate driver.
