Table of contents
Experimental chip: xc7a100tlc sg324-2L
Experimental principle
source code
`timescale 1ns / 1ps
module Shift_Register(
input CR_, CLK,
input [1:0] S,
input SR, SL,
input [7:0] D,
output reg [7:0] Q
);
always @(negedge CR_ or posedge CLK)
begin
if(!CR_)
begin
Q <= 8'bzzzzzzzz;
end
else if (S[1:0] == 2'b00)
begin
Q <= Q;
end
else if(S[1:0] == 2'b01)
begin
Q <= {Q[6:0], Q[7]};
Q[7] <= SR;
end
else if(S[1:0] == 2'b10)
begin
Q <= {Q[0], Q[6:1]};
Q[0] <= SL;
end
else if(S[1:0] == 2'b11)
begin
Q <= D;
end
end
endmodule
emulation code
`timescale 1ns / 1ps
module Shift_Register_sim;
reg [1:0] S;
reg [7:0] D;
reg CR_;
reg CLK;
reg SR;
reg SL;
wire [7:0] Q;
Shift_Register_sim uut (
.S(S),
.D(D),
.CR_(CR_),
.CLK(CLK),
.SR(SR),
.SL(SL),
.Q(Q)
);
always
begin
#10 CLK = ~CLK;
end
initial begin
S = 2'b00;
D = 8'b00000000;
CR_ = 0;
CLK = 0;
SR = 1;
SL = 1;
#20; CR_ = 0; S = 2'b01;D = 8'b11011101;
#20; CR_ = 1; S = 2'b00;D = 8'b11011101;
#20; CR_ = 1; S = 2'b01;D = 8'b11011101;
#20; CR_ = 1; S = 2'b10;D = 8'b11011101;
#20; CR_ = 1; S = 2'b11;D = 8'b11011101;
end
endmodule
pin configuration
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U17} [get_ports CLK]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V5} [get_ports CR_]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T4} [get_ports S[1]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V6} [get_ports S[0]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T5} [get_ports SR]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T6} [get_ports SL]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN R11} [get_ports D[7]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U12} [get_ports D[6]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T13} [get_ports D[5]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V14} [get_ports D[4]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T14} [get_ports D[3]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V15} [get_ports D[2]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN R15} [get_ports D[1]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U16} [get_ports D[0]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U6} [get_ports Q[7]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN R5} [get_ports Q[6]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U7} [get_ports Q[5]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN R6} [get_ports Q[4]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN R7} [get_ports Q[3]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN U8} [get_ports Q[2]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN T8} [get_ports Q[1]]
set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN V9} [get_ports Q[0]]