1. CAN protocol
1.1 Introduction to CAN protocol
CAN is the abbreviation of Controller Area Network. It was developed by German BOSCH company, which is famous for R&D and production of automotive electronic products, and finally became an international standard (ISO11519 and ISO11898). It is the most widely used field in the world. one of the buses. The differences are as follows:
1.2 CAN physical layer
CAN communication is not synchronized by clock signal, it is a kind of asynchronous communication, which only has two signal lines CAN_High and CAN_Low, which together form a set of differential signal lines and communicate in the form of differential signals
There are two main forms of the CAN physical layer
- High speed and short distance according to ISO11898 standardclosed loop network, the maximum length of the bus is 40m, the maximum communication speed is 1Mbps, and a 120 ohm resistor is required at both ends of the bus
- It is a low-speed, long-distanceopen loop network, the maximum transmission distance is 1km, and the maximum communication rate is 125kbps. The two buses are independent and do not form a closed loop. A 2.2 kohm resistor is required to be connected in series on each bus.
The circuit schematic diagram using the TJA1050 chip as the CAN transceiver is shown below.
Differential signals are also called differential mode signals. When differential signals are transmitted, two signal lines are required. The amplitudes of these two signal lines are equal and the phases are opposite. Through the two signal lines The voltage difference to represent logic 0 and logic 1,In CAN, the dominant level (the difference is positive) corresponds to logic 0, the recessive level (the difference is less than or equal to 0) corresponds to logic 1, and the dominant level is stronger than the recessive level
1.3 CAN protocol layer
CAN belongs to asynchronous communication, there is no clock signal line, each node connected in the same bus network will be like serial port asynchronous communication, and the agreed baud rate is used for communication between nodes, CAN usesbit synchronizationAnti-jamming and absorbing errors in a way to achieve correct sampling of bus level signals and ensure normal communication
- Bit timing decomposition: In order to achieve bit synchronization, the CAN protocol decomposes the timing of each data bit into SS segment, PTS segment, PBS1 segment, and PBS2 segment. The length of these four segments adds up to the length of a CAN data bit. The smallest time unit after decomposition is Tq, and a complete bit consists of 8~25 Tq
| section name | effect | Tq数 |
|---|---|---|
| SS segment (SYNC SEG) | Synchronous segment, if the communication node detects that the transition edge of the signal on the bus is included in the range of the SS segment, it means that the timing of the node and the bus is synchronous | 1Tq |
| PTS segment (PROP SEG) | The propagation period is used to compensate the physical delay time of the network. Twice the Sum of Input Comparator Delay and Output Driver Delay on the Bus | 1~8Tq |
| PBS1 segment (PHASE SEG1) | The phase buffer segment is mainly used to compensate the error of the edge phase, and its time length can be extended during resynchronization | 1~8Tq |
| PBS2 段 (PHASE SEG2) | Another phase buffer segment, also used to compensate for edge phase errors, whose duration can be shortened during resynchronization | 2~8Tq |
- Baud rate: Each communication node on the bus can determine the baud rate of CAN communication as long as the time length of 1 Tq and how many Tq each data bit occupies are agreed.
For example, assuming that 1Tq=1us in the above figure, and each data bit is composed of 19 Tq, it takes time T1bit=19us to transmit one bit of data, so the number of data bits that can be transmitted per second is: 1x10 power/19 = 52631.6 (bps). The number of data bits that can be transmitted per second is the baud rate in communication.
- Synchronization process: The baud rate only stipulates the length of each data bit, and the data synchronization also involves the details of the phase. At this time, the SS, PTS, PBS1 and PBS2 segments in the data bit are used. According to the difference in the application method of the segment, CAN data synchronization is divided into hard synchronization and re-synchronization. Among them, hard synchronization only works when there is a frame start signal, and cannot ensure that the subsequent series of bit timings are synchronized, and the resynchronization method can solve this problem
Hard synchronization: When the CAN node sends data through the bus, it will send a frame start signal. When the nodes mounted on the CAN bus are not sending data, they will always detect the signal on the bus. As shown in the figure below, when the frame start signal appears on the bus, the node detects that the frame start signal of the bus is not within the range of the SS segment of the internal timing of the node, so it judges that its own internal timing is not synchronized with the bus, so the sampling point of this state is collected data is incorrect. Therefore, the node is adjusted by hard synchronization, and the SS segment in its own bit timing is shifted to the part where the falling edge of the bus appears to obtain synchronization. After synchronization, the sampling point can collect correct data
Re-synchronization: The previous hard synchronization only works when there is a frame start signal. If there is a phase shift between the node signal and the bus signal within a long frame of data, this synchronization method is powerless. Therefore, a re-synchronization method is introduced, which uses the high-to-low transition edge of the common data bit to synchronize. Similar to the hard synchronization method, they all use the SS segment to detect, and the purpose of synchronization is to make the SS segment in the node include the jump edge. Resynchronization is divided into two cases, leading and lagging, which are distinguished by the relative position of the bus transition edge and the SS segment.
- Phase lead: The node detects that its internal timing is 2Tq ahead of the bus timing from the edge transition of the bus. At this time, the controller increases the time length of 2Tq in the PBS1 segment of the next bit timing, so that the node and the bus timing are reconnected. Synchronize.
- Phase lag: The node detects that its timing is 2Tq behind the bus timing from the edge transition of the bus. At this time, the controller reduces the time length of 2Tq in the PBS2 segment of the previous bit timing to obtain synchronization.
- Message type and structure: Pack data, operation commands (such as read/write) and synchronization signals, and the packaged content is called a message. CAN specifies 5 types of frames in total
The structure of the data frame: the data frame is the most important and complex message in CAN communication, and its structure is as follows
| section name | effect | Remark |
|---|---|---|
| start of frame | SOF, used to notify each node that there will be data transmission | 1 data bit (dominant level) |
| arbitration segment | Determine the priority of data frame transmission, and also determine whether other nodes will receive this data frame. Standard format 11 bits, extended format 29 bits | The RTR bit identifies whether a remote frame (0 data frame; 1 remote frame), the IDE bit is an identifier selection bit (0 standard identifier; 1 extended identifier), and the SRR bit is a replacement remote request bit (recessive bit), replacing RTR bit in standard frame |
| control segment | Represents the number of bytes in the data segment, consisting of 6 bits | The standard frame and the extended frame are different, r1 and r0 are reserved bits, the default is the dominant bit; DLC is the data length code, which consists of 4 bits, indicating how many bytes the data segment in this message contains |
| data segment | The original message to be sent by the node | Composed of 0~8 bytes, output from the highest bit (MSB) |
| CRC segment | Used to check for frame transmission errors | Consists of a 15-bit CRC sequence and a 1-bit CRC delimiter (bit for separation) |
| ACK segment | Used to confirm whether the normal reception | Consists of ACK slot (ACK Slot) and ACK delimiter 2 bits |
| end of frame | EOF, 7 recessive bits sent by the sending node to indicate the end | 7 data bits (recessive level) |
Other message structures
2. CAN controller
The chip of STM32 has bxCAN controller (Basic Extended CAN), which supports CAN protocol 2.0A and 2.0B standards. The CAN controller supports the highest communication rate of 1Mb/s; it can automatically receive and send CAN messages, and supports messages using standard IDs and extended IDs; there are 3 sending mailboxes in the peripheral, and the priority of sending messages It can be controlled by software, and can also record the sending time; there are 2 receiving FIFOs with 3 levels of depth, and the filtering function can be used to only receive or not receive messages with certain ID numbers; it can be configured as automatic retransmission; DMA is not supported Send and receive data. The frame diagram is as follows:
STM32 has two sets of CAN controllers, of which CAN1 is the master device. The "storage access controller" in the block diagram is controlled by CAN1. CAN2 cannot directly access the storage area, so the CAN1 peripheral clock must be enabled when using CAN2. The block diagram mainly includes the CAN control core, sending mailbox, receiving FIFO and acceptance filter, and each part of the block diagram is introduced below.
2.1 CAN control core
- Master control register CAN_MCR: responsible for managing the working mode of CAN
INRQ bit: Used to control the initialization request. When CAN is initialized, first set this bit to 1 for initialization, and then set this bit to 0 to let CAN enter the normal working mode
- Bit timing register CAN_BTR: used to configure test mode, baud rate, and segment parameters in various bits
| bit name | effect | Remark |
|---|---|---|
| THE EYE | silent mode | 0: normal work 1: silent mode |
| LBKM | loopback mode | 0: Disable loopback mode 1: Enable loopback mode |
| SJW | Resync Jump Width | The maximum number of time slices by which bits can be lengthened or shortened when resynchronizing |
| TS2 | time period 2 | Equivalent to PBS2 |
| TS1 | time period 1 | Equivalent to PTS + PBS1 |
| BRP | Baud Rate Prescaler | Used to configure the length Tq of a single time slice |
Calculation formula of CAN baud rate: You only need to know the settings of BS1 and BS2, and the clock frequency of APB1, you can easily calculate the baud rate. For example, if you set TS1=9, TS2=5 and BRP=6, under the condition that APB1 frequency is 45Mhz, you can get the baud rate of CAN communication=45000/6/(5+9+1)=500Kbps
2.2 CAN send email
CAN has 3 sending mailboxes in total, that is, it can buffer up to 3 messages to be sent. Each sending mailbox contains an identifier register CAN_TIxR, a data length control register CAN_TDTxR and two data registers CAN_TDLxR and CAN_TDHxR, as shown in the figure below
When using the CAN peripheral to send a message, it is necessary to decompose each segment of the message, write it into these registers according to the position, and set the transmission request register bit TMIDxR_TXRQ in the identifier register CAN_TIxR to 1, and then the data can be sent out . The STDID register bit in the identifier register CAN_TIxR is special. We know that the total number of CAN standard identifiers is 11 bits, while the total number of extended identifiers is 29 bits. When the message uses an extended identifier, STDID[10:0] in the identifier register CAN_TIxR is equivalent to the EXTID[18:28] bits, which together with EXTID[17:0] form a complete 29-bit extended identifier .
- Transmit mailbox identifier register CAN_TIxR
| name | effect |
|---|---|
| STID[10:0]/EXID[28:18] | MSB of standard identifier or extended identifier |
| EXID[17:0] | LSB of the extension identifier |
| IDE | Defines the identifier type for messages in the mailbox |
| RTR | Remote transmission request |
| TXRQ | Send email request |
- Send mailbox data length and time stamp register CAN_TDTxR
| name | effect |
|---|---|
| TIME[15:0] | Message timestamp with 16-bit timer value captured at SOF transmission |
| TGT | Send the global time, this bit will be active only when the hardware is in time-triggered communication mode |
| DLC[3:0] | Defines the number of data bytes in a data frame or remote frame request |
- Send mailbox low byte data register CAN_TDLxR
- Send mailbox high byte data register CAN_TDHxR
2.3 CAN receive FIFO
CAN has 2 receive FIFOs in total, and each FIFO has 3 mailboxes, that is, it can buffer up to 6 received messages. When a message is received, the message counter of the FIFO will increase by itself, and after the STM32 internally reads the FIFO data, the message counter will decrease by itself. The value of the message counter can be known through the status register, and the value of the message counter can be known through the previous main control register. The RFLM bit can be used to set the lock mode. In the lock mode, when the FIFO overflows, the new message will be discarded. In the non-lock mode, the new message will overwrite the old message when the FIFO overflows. Similar to the sending mailbox, each receiving FIFO contains an identifier register CAN_RIxR, a data length control register CAN_RDTxR and two data registers CAN_RDLxR and CAN_RDHxR, and their functions are shown in the table below
After knowing that the receive FIFO has data through the interrupt or status register, we can read the values of these registers to load the received message into the STM32 memory
- Receive FIFO Mailbox Identifier Register CAN_RIxR
| name | effect |
|---|---|
| STID[10:0]/EXID[28:18] | MSB of standard identifier or extended identifier |
| EXID[17:0] | LSB of the extension identifier |
| IDE | Defines the identifier type for messages in the mailbox |
| RTR | Remote transmission request |
- Receive FIFO mailbox data length and time stamp register CAN_RDTxR
| name | effect |
|---|---|
| TIME[15:0] | Message timestamp with 16-bit timer value captured at SOF transmission |
| FMI[7:0] | filter match index |
| DLC[3:0] | Define the number of data bytes contained in the data frame, and the remote frame is 0 |
- Receive FIFO mailbox low byte data register CAN_RDLxR
- Receive FIFO mailbox high byte data register CAN_RDHxR
2.4 CAN Acceptance Filter
CAN 验收筛选器，共有 28 个筛选器组，每个筛选器组有 2 个寄存器，CAN1 和 CAN2 共用筛选器。CAN 协议中，消息的标识符与节点地址无关，但与消息内容有关。因此，发送节点将报文广播给所有接收器时，接收节点会根据报文标识符的值来确定软件是否需要该消息，为了简化软件的工作，STM32 的 CAN 外设接收报文前会先使用验收筛选器检查，只接收需要的报文到 FIFO中。筛选器工作的时候，可以调整筛选 ID 的长度及过滤模式。
根据筛选 ID 长度来分类有有以下两种：
-
检查 STDID[10:0]、EXTID[17:0]、IDE 和 RTR 位，共 31 位
-
检查 STDID[10:0]、RTR、IDE 和 EXTID[17:15]，共 16 位
根据过滤的方法分为以下两种模式：
-
标识符列表模式，它把要接收报文的 ID 列成一个表，要求报文 ID 与列表中的某一个标识符完全相同才可以接收，可以理解为白名单管理。
-
掩码模式，它把可接收报文 ID 的某几位作为列表，这几位被称为掩码，可以把它理解成关键字搜索，只要掩码 (关键字) 相同，就符合要求，报文就会被保存到接收 FIFO。
通过配置筛选模式寄存器 CAN_FM1R 的 FBMx 位可以设置筛选器工作在哪个模式。通过配置筛选尺度寄存器 CAN_FS1R 的 FSCx 位可以设置筛选器工作在哪个尺度。不同的尺度和不同的过滤方法可使筛选器工作在图 的 4 种状态。
每组筛选器包含 2 个 32 位的寄存器，分别为 CAN_FxR1 和 CAN_FxR2，它们用来存储要筛选的ID 或掩码，各个寄存器位代表的意义与图中两个寄存器下面“映射”的一栏一致，各个模式的说明见表
例如下面的表格所示，在掩码模式时，第一个寄存器存储要筛选的 ID，第二个寄存器存储掩码，掩码为 1 的部分表示该位必须与 ID 中的内容一致，筛选的结果为表中第三行的 ID 值，它是一组包含多个的 ID 值，其中 x 表示该位可以为 1 可以为 0。
When working in the identifier mode, the two registers store the ID to be filtered, and it only contains two ID values to be filtered (in 32-bit mode). If filters are enabled and the message's ID does not match any filter configuration, the CAN peripheral discards the message without storing it in the receive FIFO.
- Filter Mode Register CAN_FM1R
| name | effect |
|---|---|
| FBMx | 0: The two 32-bit registers of filter bank x are in identifier mask mode. 1: The two 32-bit registers of filter bank x are in identifier list mode. |
- Filter scale register CAN_FS1R
| name | effect |
|---|---|
| FSCx | 0: Double 16-bit standard configuration; 1: Single 32-bit standard configuration |
- Filter FIFO Allocation Register CAN_FFA1R
| name | effect |
|---|---|
| FFAx | Filter FIFO allocation for filter x, messages passing this filter will be stored in the specified FIFO |
- Filter Activation Register CAN_FA1R
| name | effect |
|---|---|
| ACTx | Filter active, software sets this bit to activate filter x |
- register x CAN_FiRx for filter bank i
| name | effect |
|---|---|
| FB[31:0] | filter bits |
After introducing the basic knowledge of CAN, the CAN communication example of the STM32 chip will be introduced in the follow-up article