overload frame
Overload frames have the same format as active error frames. However, overload frames can only be generated in the interframe space, so overload frames can be distinguished from error frames (error frames are sent when the frame is transmitted) in this way. The overload frame consists of two fields, the overload flag followed by the overload delimiter. The overload flag consists of 6 dominant bits followed by the overload flag generated by other nodes (while the active error flag contains up to 12 dominant bits). The overload delimiter contains 8 recessive bits. A node generates overload frames in two situations:
1. The node detects an illegal dominant bit in the inter-frame interval. The exception is that the dominant bit is detected during the third bit of IFS. In this case, the receiver will see it as a SOF signal.
2. Due to internal reasons, the node cannot start to receive the next message. A node can generate up to two consecutive overload frames to delay the sending of the next message.
Interframe space
The interframe space separates the previous frame (of whatever type) from the following data frame or remote frame. The inter-frame interval consists of at least 3 recessive bits, also known as a discontinuity. Interruptions give nodes time to do internal processing before sending the next message. After the break, the CAN bus will remain in a recessive state (bus idle) until the next message begins to be sent.
Bit sequential logic
Bit Timing Logic (BTL) monitors bus inputs and handles bus-related bit timing operations according to the CAN protocol. The BTL performs a synchronous operation (called hard synchronization) on the bus transition from the recessive state to the dominant state at the start of the frame. If the CAN controller itself does not send dominant bits, then a subsequent recessive-to-dominant bus transition occurs (called resynchronization) again. The BTL also provides programmable time periods to compensate for propagation delay times and phase shifts, and defines the sampling point positions within the bit period. Programming the BTL depends on the baud rate and external physical delay time.
Copyright ownership belongs to Qingcui Technology Hangzhou FPGA Division , please indicate the source for reprinting
Author: Hangzhou Qingcui Technology ALIFPGA
Original address: Hangzhou Qingcui Technology FPGA Geek Space WeChat Official Account
Scan the QR code to follow Hangzhou Qingcui Technology FPGA Geek Space