FPGA底层资源主要是Slices、IOBs、Memory、Multipliers、Global clock buffers等等，下面对各类资源进行详细的解读。
1. Slices
The slice of the 7 series FPGA consists of 4 parts:
(1)
The logic function generator, which is what we often call the lookup table LUT, contains 4 6-input lookup tables in one slice.
(2)
The storage unit, which is often referred to as a flip-flop, contains 8 flip-flops in one slice. Each group of 4 flip-flops can be configured as D flip-flops or latches.
(3)
The multiplexer, that is, the 1-bit wide data selector mux, is very large in number and is sufficient for use.
(4)
carry logic (carry chain), and this is not an OR gate, but an XOR gate. This is the carry chain (Carry Chain) logic that comes with the FPGA. Generally, when you implement a design such as a counter that may have carry logic, this part of the resource may be called.
Therefore, the combination of many slices and the global clock can realize complex digital functions!
Structural diagram of sliceL:
2. The function of IOBs
programmable IO is to complete the acquisition and output of signals. The pins can be configured to support different electrical characteristics, pull-up and pull-down or tri-state, differential or single-ended. The IOB and nearby resources such as idelay, odelay, ilogic, ologic, and programmable IO together form the IO_Bank of the FPGA.
3. Memory
The on-chip memory of FPGA can generally be divided into two types, namely Distributed RAM and Block RAM. DRAM is implemented by LUT, and Block RAM is a dedicated mem resource with a larger capacity than DRAM.
In the UltraScale+ series, Xilinx introduced a new dedicated mem resource called Ultra RAM. The capacity of a single URAM is 6 times that of Block RAM, which can support greater data processing requirements. Use the table below to compare the three Mem resources. For more detailed content, you can read the Xilinx Guide
to store the same data. Using BRAM may consume less resources than DRAM, but BRAM may have a greater impact on timing. If timing is a more important factor at this time, you have to sacrifice Drop some resources to use DRAM.
Reference: "UltraScale Architecture Memory Resources"
"UltraScale Architecture Configurable Logic Block"
Four. Multipliers
multiplier, as the name suggests, is used for multiplication
5.
The introduction of FPGA clock resources is mainly divided into three parts. The first part is the area structure, the second part is the component function, and the third part is the implementation.
First of all, the clock resources of the FPGA are responsible for driving all sequential logic. Manufacturers try their best to make the clock resources sufficient and reliable. In order to achieve this goal, xilinx adopts a structured clock resource layout method.
First divide the entire board into two parts, the left and right, with exactly the same width, and the main artery in the middle. That is, the Clocking Backbone at the Clocking Center position in the figure below, and all BUFG (Global Clock buffers) are also included in it.
As the name suggests, BUFG is the global Clock buffer.
BUFG can
1. As a clock enable to control the clock across several clock domains
2. As a glitch-free multiplexer to select one of the two clocks or switch out the failed clock
3. Driven by CMT to eliminate clock distribution Delay, adjust the delay relative to another clock
One artery obviously cannot supply blood to the whole human body, and the limited number (7 series has 32 wiring resources) BUFG cannot directly drive all logic resources. Although BUFG has the widest driving range, it is not possible to obtain the best results by using BUFG for all resources.
So we also need horizontal blood vessels, that is, HROW (Horizontal Clock Row), which are equidistant and horizontally distributed, very similar to the chessboard layout when building roads in a simulated city. But HROW is different from Clock Backbone. They are mainly responsible for the timing logic resource drive of the adjacent upper and lower parts. The specific implementation is through BUFH. BUFH is equivalent to the castrated version of BUFG. There are 12 BUFH routing resources in each clock domain, that is, a clock domain can use up to 12 BUFH routing resources to introduce 12 BUFG clocks.
It is also emphasized here that all global clock signal lines must pass through the Clock Backbone when routing, and when the global clock signal line comes out of the Clock Backbone and enters a specific clock region, it must pass through HROW. Then we can conclude that all global clock lines must go through Clock Backbone and HROW when routing, and BUFG and BUFH share the routing resources in HROW. A path into a certain clock domain can be a BUFG signal line drawn from the Clock Backbone, and then connected to the BUFH. A total of BUFG wiring resources (1/32) and (1/12) are used. Of course, the signal Lines are reusable.
What is the clock region? The clock area is the division of the board, and its upper and lower boundaries are in the middle of two HROWs, that is to say, there is an HROW across the middle of each clock area. And its left and right boundaries are the middle of the two CMT Backbone. Similarly, there is a CMT Backbone vertically passing through the middle of each clock area. Depending on the size of the board, the number of clock domains varies from 1 to 24. A clock domain includes all synchronous components (CLB, I/O, serial transceivers, DSP, block RAM, CMT). Each clock domain includes 50 CLBs and 1 I/O bank (50 I/Os).
In addition to horizontal blood vessels, we also need small blood vessels and capillaries, corresponding to BUFMR and BUFR. BUFMR can drive all timing resources in this clock domain and the two adjacent clock domains up and down. When it drives adjacent clock domains, the routing needs to go through the CMT Backbone. And BUFR can only drive timing resources in this clock domain.
And BUFIO can only drive the I/O components in this clock domain/this I/O domain.
Reference: https://blog.csdn.net/weixin_43778388/article/details/122521139
https://zhuanlan.zhihu.com/p/336370365?utm_medium=social&utm_oi=47239162494976
http://t.zoukankan.com/aliothx- p-13398060.html
https://blog.csdn.net/dongdongnihao_/article/details/111354406
https://blog.csdn.net/wenjia7803/article/details/115339122