Insufficient BRAM resources? Don't be afraid! Here are some tips for saving FPGA BRAM resources!

FPGA resources such as BRAM and LUT are limited. During the FPGA development process, you may often encounter situations where BRAM or LUT resources are insufficient.

It is generally recommended that the consumption of BRAM and LUT resources should not exceed 80%. Of course, higher-end FPGA chips can also be relaxed to 90%. If this limit is exceeded, serious timing violations may occur, resulting in abnormal board operation.

Today I will share a BRAM resource usage optimization strategy, taking Vivado’s Block Memory Generator as an example.

1. Distribute BRAM or URAM instead of BRAM

The storage depth and width are small, and LUT resources or URAM are abundant, so you can use "Distribute BRAM" or "URAM" instead.

Here you need to pay attention to the FPGA chip model used and whether it has URAM resources.

• (*ram_style = "block" *) means using Block RAM to implement

• (*ram_style = "reg" *) means using registers to implement

• (*ram_style = "distributed" *) indicates that it is implemented with distributed RAM

• (*ram_style = "uram" *) means using uram to implement

Code examples are given here:

// FPGA 双口 RAM
module dual_port_ram(
  input clk,
  input [7:0] data_in, 
  input [5:0] wr_addr,
  input wr_en,

  input [5:0] rd_addr,
  output reg [7:0] data_out
);

// 声明双口 RAM 存储器  
(* ram_style = "block" *)reg [7:0] ram[63:0];  

// 时钟上升沿写入  
always @(posedge clk) begin
  if (wr_en) 
    ram[wr_addr] <= data_in; 
end 

// 读取;  
always @(posedge clk) begin
  data_out <= ram[rd_addr]; 
end

endmodule

2. Dual-port ROM replaces single-port ROM

If there are more than two ROMs or RAMs in the project that use the same data, you can use dual-port instead of single-port mode. The resource consumption is the same, so you can save one or more ROM IPs.

Here is a comparison of the resource consumption in single-port and dual-port modes with "data width of 32 and storage depth of 1024".

3. Reasonable data width and depth settings

In order to optimize FPGA BRAM resource consumption, it is more critical to optimize the cache size design of the FPGA project, calculate the bit width and maximum depth of the theoretical cache data, and select appropriate parameters.

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