Memory access:
LDR/LDRB Rd, =LABLE; load the address corresponding to the symbol LABLE and store it in Rd
LDR/LDRB Rd, [Rs]; Take the address from the Rs register, read the corresponding 32-bit/8-bit data, and store it in the Rd register
STR/STRB Rd, [Rs]; Take the address from the Rs register and store the 32-bit/8-bit data in Rd to the corresponding address
Bulk memory access:
LDMIA Rd!,{Rn,...,Rm}; Read 32-bit data from Rd by increasing the address multiple times, and store it to the Rn,...,Rm register list
STMDB Rd!,{Rn,...,Rm}; 32-bit data is stored in consecutively decremented addresses from Rd, and the data comes from the Rn,...,Rm register list
Explanation: IA (Increase After): Increment the address after the operation is complete
DB (Decrease Before): decrements the address before the operation starts
! : After the operation, save the final address to the register Rd
MSR and MRS - for accessing xPSR, PSP, MSP, etc.:
MRS Rn, <SReg>; load the value of the energy register to Rn
MSR <SReg>, Rn; store the value of Rn into the enable register
Interrupt switch:
CPSID I; close interrupt
CPSIE I; open interrupt
Unconditional jump:
BX Rn; move to the address given by the register Reg, such as BX LR can be used for the return of the subroutine
Compare jump:
CBZ Rn,<lable>; If the Rn register value is 0, jump to the instruction corresponding to the lable, otherwise execute the next instruction
CBNZ Rn,<lable>; If the Rn register value is not 0, jump to the instruction corresponding to lable, otherwise execute the next instruction
Logical OR Operation:
ORR Rd,Rn,#imm12; is equivalent to Rd = Rn | imm12