- CE: module control line, when CSN is low, CE cooperates with the CONFIG register to determine the state of NRF24L01
- CSN: SPI chip select line
- SCK: SPI clock line
- MOSI: SPI data line (master output slave input)
- MISO: SPI data line (master input slave output)
- IRQ: Interrupt signal line. Changes to low level when interrupted, and becomes low in the following three situations: Tx FIFO is sent and ACK is received (when ACK is enabled), Rx FIFO receives data, and the maximum number of retransmissions is reached
In idle state, SCK is 0, CPOL=0; data is collected at the first transition edge of the clock, CPHA=0;
- Cn: SPI command bit
- Sn: STATUS register bit
- Dn: data bit (MSB, low byte first in multi-byte transmission)
3. Working mode
NRF24L01 working mode, controlled by PWR_UP (bit 1) and PRIM_RX (bit 0) of CE and CONFIG registers (0x00):
| NRF24L01 working mode | PWR_UP bit status | PRIM_RX bit status | CE pin level | FIFO register status |
|---|---|---|---|---|
| receive mode | 1 | 1 | 1 | - |
| send mode | 1 | 0 | 1 | Data is in the TX FIFO register |
| send mode | 1 | 0 | 1 ----> 0 | Stay in send mode until sending |
| Standby Mode II | 1 | 0 | 1 | TX FIFO is empty |
| Standby mode I | 1 | - | 0 | no data transfer |
| Power-down mode | 0 | - | - | - |
- Enhanced ShockBurstTM transceiver mode
At the receiving end , the address is recorded after confirming that the data is received, and a response signal is sent with this address as the target address. At the sending end , channel 0 is used as the receiving response signal, so the receiving address of channel 0 is equal to the sending address end address to ensure that the correct response signal is received.
Enhanced ShockBurstTM sending process:
A. Send the address and the data to be sent to NRF24L01 in time;
B. Configure the CONFIG register to enter the sending mode;
C. MCU sets CE high (at least 10us) to stimulate Enhanced ShockBurstTM transmission ;
D. Enhanced ShockBurstTM transmission: a) Supply power to the RF front-end;
b) Pack the RF data (add header and CRC check code);
c) Transmit data packets at high speed;
d) After the transmission is completed, the NRF24L01 enters the idle state
Enhanced ShockBurstTM receiving process:
A. Configure the receiving address and the size of the data packet to be received;
B. Configure the CONFIG register to enter the receiving mode and set CE high;
C. After 130us, the NRF24L01 enters the monitoring state and waits for the arrival of the data packet;
D. When receiving To the correct data packet (correct address and CRC check code), NRF24L01 automatically removes the header, address and CRC check bit
E. NRF24L01 informs the MCU by setting the RX_DR of the STATUS register (STATUS generally causes MCU interruption);
F. MCU reads data from FIFO (0x61 command);
G. After all data is read, the STATUS register can be cleared; NRF24L01 can enter one of the four main modes.
4. SPI command
| command name | Instruction format | operate |
|---|---|---|
| R_REGISTER | 000A AAAA | Read registers. AAAAA is the register address to be read |
| W_REGISTER | 001A AAAA | write register. AAAAA is the register address to be written |
| R__RX_PAYLOAD | 0110 0001 | Read RX valid data, 1-32 bytes. The read operation starts from byte 0, when the RX valid number is read After the data is completed, the valid data in the FIFO register will be cleared. Used in receive mode. |
| W_TX_PAYLOAD | 1010 0000 | Write TX valid data, 1-32 bytes. The write operation starts from 0 bytes and is used in transmit mode. |
| FLUSH_TX | 1110 0001 | Clear the TX FIFO register. Use in send mode |
| FLUSH_RX | 1110 0010 | Clear the RX FIFO register. Use in receive mode |
