DDR3: usage flow
1. Configuration process
1> First find the IP core
2> Select the compatible chip, this ddr is compatible with the three chips of the K7 series
3> Select ddr3
4> Configure the working clock part
Before configuring the clock, let’s first understand the clock relationship of the ip core of ddr3 , as shown below, a total of three clocks. The working clock and reference clock of the IP core must be directly connected to the circuit board and cannot be obtained by dividing the frequency of the IP core.
Common frequency of working clock of IP core: 50M/200M (no need to select reference clock)
①: Adjust the DDR3 working clock by cycle
②: 4:1 and 2:1 part, is to select the user's working clock
4:1 means that the user clock is 100M
when the DDR3 working clock is 400M; 2:1 means that the DDR3 working clock is 400M In this case, the user clock is 200M
③: Select the DDR3 device model
④: Select the bit width of the data, which needs to be determined according to the device, such as 64M*16bit=128M ddr3 chip, the bit width of the two pieces is 32bit
⑤: Indicates the data mask , similar to the keep line.
⑥: The number of DDR3 banks
5> Configure the IP core clock
① means: the working clock of the IP core, the common clock is 50M, 200M (the reference clock can not be selected) must be directly connected to the board
② means: data sequence
③ means: address type
6> continue Configure the clock
① Select the input method of the system clock: single-ended or differential
② Select the reference clock, if you select the 200M system clock, you can directly use the system clock as the reference clock without selecting the reference clock
③ Select the reset high and low effective
7> This configuration pin is
8 >Configuration pins
are : signal name (determined by the schematic diagram)/bank number/byte number/pin number/then check it and
assign the reference clock pin
2. ip core pin description
pin name |
Pin Orientation |
Remark |
ddr3_addr |
output |
|
ddr3_ba |
output |
|
ddr3_cas_n |
output |
|
ddr3_ck_n |
output |
|
ddr3_ck_p |
output |
|
ddr3_cke |
output |
|
ddr3_ras_n |
output |
|
ddr3_reset_n |
output |
reset status signal |
ddr3_we_n |
output |
|
ddr3_dq |
inout |
|
ddr3_dqs_n |
inout |
|
ddr3_dqs_p |
inout |
|
init_calib_complete |
output |
initialization complete signal |
ddr3_cs_n |
output |
|
ddr3_dm |
output |
|
ddr3_odt |
output |
|
|
|
|
app_addr |
input |
To operate the address each time step is 8 |
app_cmd |
Input |
write 000 read 001 |
app_en |
Input |
enable signal |
app_wdf_data |
input |
Written data [255:0] |
app_wdf_end |
input |
last |
app_wdf_wren |
input |
write enable |
app_rd_data |
output |
Read data【255:0】 |
app_rd_data_end |
output |
A rising edge last in the last line |
app_rd_data_valid |
output |
read valid |
app_rdy |
output |
|
app_wdf_rdy |
output |
|
app_sr_req |
input |
assign 0 |
app_ref_req |
input |
assign 0 |
app_zq_req |
input |
assign 0 |
app_sr_active |
Output |
|
app_ref_ack |
Output |
|
app_zq_ack |
Output |
|
ui_clk |
output |
Usr's always clock |
ui_clk_sync_rst |
output |
Usr reset signal |
app_wdf_mask |
input |
Keep signal |
|
|
|
sys_clk_i |
input |
Directly connected to the board clock |
clk_ref_i |
input |
Directly connected to the board clock |
sys_rst |
input |
Direct Connect Board Subsystem Reset |
|
|
|
|
|
|
3. Timing analysis
1> Write timing: After both app_rdy and app_wdf_ready are pulled high, the operation can be performed. Issue the write data cmd and pull an app_en to input the written data and address at the same time. It is worth noting that the DDR allows the write enable signal to be within two clocks behind the cmd. But it is still recommended to write data and addresses within one cycle
2>Read timing
First issue the read command, and pull up an app_en and addr at the same time. Then wait for a valid signal and wait to read the data. Instructions in the next few cycles return data in several cycles.
4. Effect
Do a program to write all F data to AADR0, and then read it out. The effect is as follows:
