Cortex-M3 internal registers

register bank

R0-R12

R0-R12, general-purpose registers; 
R0-R12 are 32-bit general-purpose registers for data operations; but most 16-bit Thumb instructions can only access R0-R7, while 32-bit Thumb instructions can access all registers;

R13

R13, SP, stack pointer; 
Cortex-M3 has two stack pointers, they are Banked, and only one of them can be used at any time; when referring to R13/SP, it refers to the one currently being used, and the other must be used MRS/MSR instructions to access; 
- Main stack pointer MSP: default stack pointer after reset, used for operating system kernel operations and exception handling routines; 
- Process stack pointer PSP: used by user application code; 
the lowest stack pointer Two bits are always 0, which means the stack is always 4-byte aligned;

R14

R14, LR, link register; 
when a subroutine is called, the return address is stored by R14; if the subroutine is more than one level, the R14 of the previous level needs to be pushed into the stack;

R15

R15, PC, the program counter register 
reads the PC value, and returns the current instruction address + 4; if you modify it, you can change the execution flow of the program; 
when branching, whether you directly write the PC or use the branch instruction, you must ensure that the load is loaded The value to the PC is an odd number (LSB=1) to indicate that it is executed in the Thumb state. If it is 0, a fault will be generated;

special function register

Special function registers must be operated by MRS/MSR instructions;

program status register

The Program Status Registers (PSRs or xPSR) can be internally divided into 3 sub-status registers: 
- Application PSR (APSR) 
- Interrupt Number PSR (IPSR) 
- Execution PSR (EPSR) 
Through the MRS/MSR instruction, these 3 PSRs can be individually Access, also combined access: 
- PSR = APSR + IPSR + EPSR 
- IAPSR = IPSR + APSR 
- IEPSR = IPSR + EPSR 
- EAPSR = EPSR + APSR

	31	30	29	28	27	26-25	24	23-20	19-16	15-10	9	8-0
APSR	N	WITH	C	V	Q
IPSR												Exception Number
EPSR						ICI/IT	T			ICI/IT

interrupt mask register

PRIMASK

This register has only one bit. When set to 1, it will close all maskable interrupt exceptions, leaving only NMI and hard fault, and the default value is 0; 
operation instructions:

MRS R0, PRIMASK        ; R0=PRIMASK
MSR PRIMASK, R0        ; PRIMASK=R0
CPSID I                ; PRIMASK=0
CPSIE I                ; PRIMASK=1

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FAULTMASK

This register also has only one bit. When set to 1, all exceptions (including hard faults) except NMI are shielded. The default value is 0; 
operation instructions:

MRS R0, FAULTMASK       ; R0=FAULTMASK
MSR FAULTMASK, R0       ; FAULTMASK=R0
CPSID F                 ; FAULTMASK=0
CPSIE F                 ; FAULTMASK=1

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BASEPRI

This register has 9 bits, which defines the threshold of the masked priority; when it is set to a certain value, all interrupts with a priority number greater than or equal to this value are closed, and if it is set to 0, no interrupts are closed. , the default value is 0;

MRS R0, BASEPRI       ; R0=BASEPRI
MSR BASEPRI, R0       ; BASEPRI=R0

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Control register (CONTROL)

• CONTROL[1]: 0 means selecting MSP, 1 means selecting PSP;
• CONTROL[0]: 0 means the thread mode of the privilege level, 1 means the thread mode of the user level;