[Biting] interrupted
when the processor in response to certain exceptions, and if other abnormalities, but they are not high enough priority, then they will be blocked.
So when, after the implementation of the current abnormal returns, the system hanging from the handle of abnormal, or if the first POP, POP and then again content processing PUSH back, then wasted CPU time. Thus, Cortex-M3 will not POP these registers, but continue to use the previous abnormality has good results PUSH, POP and PUSH operation to eliminate time-consuming.
This way, looks like an exception after a tail to the front out, back and forth only the implementation of a PUSH / POP operation. Thus, "time gap" between the two narrows many abnormal, as shown in FIG:
conventional comparison processing (the ARM7) is interrupted:
[Break] as late as
Cortex-M3 interrupts there is another mechanism to deal with, it emphasizes the priority role, which is the "exception handling late arrivals."
When a pair of Cortex-M3 abnormal response sequence is still in the early stage: when the stack stage, yet perform other service programs. If at this time received a higher priority unusual request, this push has become a high priority interrupt to do a. After the stack, it will perform high-priority exception service program. Visible, high-priority exception though late, but because of the high priority so that the service program can be processed first, low-priority anomalies stacking is turned into a high-priority anomalies of the stack.
For example, if a low priority in response to early # 1 is abnormal, a high priority is detected anomaly # 2, # 2 as long as not too late to be able to "break late" approach process, performed after the completion of Drawing ISR # 2. As shown:
If the exception # 2 too late, so that the ISR has been performed, the instruction # 1, the conventional preemption press process, which will require more time and processor 32 additional bytes of stack space. After ISR # 2 is finished, by the "tail biting break" way to start the execution of ISR # 1.
Quoting from the reference:
"Cortex-M core lecture series and STM32- 2 Tutorial .pdf"
"ARM Cortex-M3 Definitive Guide .pdf"