Table of contents
Realize CM3
assembly line
The CM3 processor uses a 3-stage pipeline, namely: fetch, decode and execute
CM3 sometimes fetches two 16-bit instructions at a time (32-bit instructions in total), processes one first and then waits a cycle before processing the next
In consideration of Thumb compatibility, when taking PC, it will return the current instruction address + 4 value
The processor core has a prefetch unit 指令缓冲区where subsequent instructions are queued
CM3 Detailed Block Diagram
| abbreviation | meaning |
|---|---|
| NVIC | Nested Vectored Interrupt Controller |
| SYSTICK Timer | A simple periodic timer used to provide a time base, also used by the operating system |
| MPU | Memory Protection Unit (optional) |
| CM3BusMatrix | Internal AHB Interconnect |
| AHB to APB | A bus bridge that converts AHB to APB |
| SW-DP/SWJ-DP | Serial Wire Debug Port/Serial Wire JTAG Debug Port. Either the serial wire debug protocol or the traditional JTAG protocol (dedicated to SWJ-DP) can be used to realize the connection with the debug interface |
| AHB-AP AHB | Access port that converts commands from the Serial Wire/SWJ interface into AHB data transfers |
| ETM | Embedded trace macrocell (optional component), for debugging. Used to process instruction trace |
| DWT | Data observation point and tracking unit, for debugging. This is a module that handles data watchpoint functionality |
| ITM | Instrumented Tracking Macrocells |
| TPIU | Interface unit for tracking unit. All debugging information sent by the trace unit must be sent to it first, and then forwarded to the external trace capture hardware. |
| FPB Flash | Address reload and breakpoint unit |
| ROM table | A small lookup table where configuration information is stored |
Introduction to each important module in the CM3 processor:
- CM3Core：CPU
- NVIC: Support interrupt nesting, the vector interrupt mechanism can automatically fetch the entry address of the corresponding service routine when an interrupt occurs
- SysTick timer: implemented inside the NVIC, can generate interrupts at regular intervals, even if the system sleeps, it can work
- Memory protection unit: divide the memory into multiple areas for protection
- BusMatrix: CM3 bus core, through which data is transmitted between different buses
- AHB to APB Bridge: a bus bridge that connects multiple APB devices to a private peripheral bus
- SW-DP/SWJ-DP: Serial debugging
- AHB-AP: None
- ETM Embedded Trace Macrocell: Real-time instruction trace,
- DWT data observation point and tracking unit: set data observation point through it
- ITM Instrumented Trace Macrocells: None
- FPB: Provide flash address reload and breakpoint functions
CM3 bus interface
I-Code 总线A 32-bit bus for instruction fetch operations
D-Code 总线A 32-bit bus for data access operations, devices connected to the bus do not need to support unaligned access
系统总线Responsible for data transmission, they are all aligned
外部私有外设总线32-bit bus based on APB protocol, responsible for private peripheral access
调试访问端口总线Dedicated to hooking the debug interface
Bus connection template
abnormal
exception type
The corresponding system exceptions numbered 1-15, and those greater than or equal to 16 are all external interrupts
Interruption does not equal exception
15 available system exception tables
priority definition
The smaller the value of the priority, the higher the priority.
CM3 supports interrupt nesting, so that high-priority exceptions will preempt low-priority exceptions
Three special system exceptions: 复位，NMI 以及硬 fault, which have a fixed priority, and their priority number is negative, thus higher than all other exceptions
CM3 also divides the 256-level priority into high and low levels according to bits, which are called抢占优先级和子优先级
There is a register in the NVIC to save the priority group, which divides the priority into two segments: the bit
segment where the MSB is located corresponds to the preemption priority; the bit segment where the LSB is located corresponds to the sub-priority
priority group
CM3 supports 8 different interrupt priorities, usually divided into 4 priority groups
Four mainstream methods of CM3 interrupt priority group assignment:
Preemptive Priority Grouping (0 位抢占优先级组):
In this mode, priority grouping is disabled, and all interrupts have unique priorities. An interrupt with a higher priority value can always interrupt an executing interrupt with a lower priority value. This is the simplest interrupt priority mode, but may not be flexible enough in complex applications.
No Preemptive Priority Grouping (4 位抢占优先级组):
In this mode, interrupts are divided into 4 priority groups, and each group has 2 priorities. Interrupts from each group will not interrupt each other, but higher priority interrupts within a group can interrupt lower priority interrupts. This provides a degree of layering and prioritization control.
Priority Grouping (3 位抢占优先级组):
In this mode, interrupts are divided into 8 priority groups, and each group has 1 priority. This means that each interrupt has a unique priority and no interrupt is completely masked by other interrupts. This provides finer-grained priority control, but may require more configuration in complex applications.
Priority Grouping (2 位抢占优先级组):
In this mode, interrupts are divided into 16 priority groups, and each group has 1 priority. This mode provides more flexibility than the above mode, but the configuration will be more complicated.
vector table
Cortex-M3The processor uses the interrupt vector table to manage the entry addresses of different interrupts.
The interrupt vector table is an array that stores the address of the interrupt handler, and each element corresponds to a specific interrupt number.
When an interrupt occurs, the processor will read the corresponding address from the vector table according to the interrupt number, and then jump to the corresponding interrupt handler.
The interrupt vector table is usually located at the start address of memory. Each element in the vector table is a 4-byte (32-bit) address pointing to the corresponding interrupt handler
A space can be opened in SRAM for storing the vector table
interrupt input on pending
NMI
NMI (Non-Maskable Interrupt, non-maskable interrupt) is a special type of interrupt, which is often used in embedded systems to handle some urgent and important events. Unlike ordinary maskable interrupts, NMIs are interrupts that cannot be masked or blocked, and can still trigger even if the processor is in a masked interrupt state (for example, global interrupts are disabled).
When NMI occurs, the processor will jump to the entry address of the NMI handler to perform corresponding operations
interrupt pending
After the interrupt input pin is set valid, it will be suspended, and the interrupt request cannot be canceled at this time.
If the suspended state is canceled before the interrupt is responded, the interrupt will be cancelled.
When an interrupt service routine starts executing, its pending status is automatically cleared by hardware
The interrupt source maintains the interrupt request signal all the time, then the interrupt will be given the pending state immediately after completing a round of service process for the next round. The
interrupt source sends N multiple interrupt request signals in the form of pulses, and finally only one will be accepted.
Fault class exception
bus faults
Possible situations where this fault occurs:
- An error signal was returned while data was being transmitted on the AHB interface
- When the vector is read after the processor initiates the interrupt service sequence (sequence)
- Stack PUSH action at the beginning of interrupt processing
- Stack POP action at the end of interrupt processing
Once the bus fault detects a higher priority exception, it will execute the latter first and hang itself
If the bus fault is caused by a service routine with an exception of the same level or higher priority, it will become a hard fault, so that the last execution is the service routine of the hard fault
Before enabling the bus fault service routine, the entry address of the bus fault service routine must have been configured in the vector table
总线 fault 状态寄存器(BFSR)Located inside the NVIC, you can find out the cause of the fault
memory management faults
There are four reasons for triggering the faults:
- Addresses outside the coverage of all MPU regions are accessed
- An empty address with no memory corresponding to it was accessed
- Write data to read-only region
- User-level access to an address that is only allowed at the privileged level
If the MemManage fault is disabled, it will appeal to hard faults.
If the execution of the hard faults causes a MemManage fault, the kernel will be locked
MemManage fault must be enabled to respond normally
Usage faults
An important feature of usage faults is that
a coprocessor instruction is executed. Cortex-M3 itself does not support coprocessor, but through the fault exception mechanism, a set of "software simulation" mechanism can be established to execute a program to simulate the function of coprocessor
The rest of the functions and the enabling and disabling conditions are basically the same as the memory faults, so I won’t introduce them too much here.
The most common cause of usage faults is: View cut into ARM state
SVC and PendSV
The OS does not allow users to directly operate the hardware, so there is a corresponding bridge SVC (system service call)
SVC can be defined as follows:
the operating system provides system service functions, and users send requests to these functions through SVC to indirectly control the hardware
SVC exceptions can be generated by executing the SVC instruction;
the SVC instruction requires an immediate value, which acts as a system call code
PendSV has the same function as SVC, except that it can be suspended
The PendSV exception handler usually saves the context of the current task and loads the context of the next task, thus achieving task switching
PendSV's task has a low priority, so it can be interrupted by many high-priority routines