1. What is ISSP? What is ISSP for?
The Quartus II software provides the In-System Sources and Probes Editor debug tool, which can be used to drive and sample the logic values of internal nodes through the JTAG interface. That is, the internal signal of the fpga is driven by the Sources function, and the logic value of the internal node is detected by the Probes function. This tool can be used to simulate numerous input stimuli before the system design is complete. For example, the value of some internal registers can be modified in real time through the IP core, without re-modifying the code, then fully compiling, and then downloading and debugging.
Generally speaking, using the ISSP IP core can provide input to the module under test, and this input can be changed online; at the same time, it can also detect the output value of the module under test (similar to Signaltap).
2. Use of ISSP
In the static display chapter of the nixie tube ( FPGA very easy introductory tutorial ---- nixie tube chapter (1) static display ), we wrote the dynamic driver code, and tested the driver code by using the method of timing data generation. This test method has high coverage, but is not flexible enough. If we use the ISSP IP core to test, we can directly modify the input online to play a specific debugging role.
1. First create a new project issp_test
2. Create a new digital tube driver file and add it to the project
//6位8段式数码管静态显示驱动
//端口定义
module dis_sta_dri (
input sys_clk , //时钟信号
input sys_rst_n , //复位信号（低有效）
input [3:0] num, //数码管显示的十进制数
output reg [5:0] dis_sel, //数码管位选
output reg [6:0] dis_seg, //数码管段选
output dis_dp //数码管小数点
);
assign dis_dp = 1'b1; //小数点，我们暂时不同，使其无效即可
//控制数码管位选信号（低电平有效），选中所有的数码管
always @ (posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
dis_sel <= 6'b111111; //复位熄灭所有数码管
else
dis_sel <= 6'b000000; //复位完成后给所有数码管供电
end
//根据数码管显示的数值，控制段选信号（低电平有效）
always @ (posedge sys_clk or negedge sys_rst_n) begin
if (!sys_rst_n)
dis_seg <= 7'b111_1111; //复位时熄灭数码管（这一条用处不大，因为复位时数码管也不供电）
else begin
case (num)
4'h0 : dis_seg <= 7'b000_0001; //显示数字“0”，则数码管的段选编码为7'b000_0001
4'h1 : dis_seg <= 7'b100_1111;
4'h2 : dis_seg <= 7'b001_0010;
4'h3 : dis_seg <= 7'b000_0110;
4'h4 : dis_seg <= 7'b100_1100;
4'h5 : dis_seg <= 7'b010_0100;
4'h6 : dis_seg <= 7'b010_0000;
4'h7 : dis_seg <= 7'b000_1111;
4'h8 : dis_seg <= 7'b000_0000;
4'h9 : dis_seg <= 7'b000_0100; //显示数字“9”，则数码管的段选编码为7'b000_0100
default : dis_seg <= 7'b111_1111; //其他数字（16进制的数字相对10进制无效）则熄灭数码管
endcase
end
end
endmodule3. Enter the IP selection interface
4. Instantiate the In-System Sources and Probes Editor IP core, the name (whichever you choose) is Sou_Pro, click Next to enter the IP parameter setting interface.
5. Set IP parameters as follows
(1) Choose whether to specify the number of the instantiated IP, the default setting, do not need to be modified
(2) Whether to set the ID number of the IP core. Because in a project, multiple In-System Sources and Probes Editor IP cores can be instantiated, and the ID number is used to distinguish different IP cores
(3) It is used to set the probe (Probes) port. The probe function is used to detect the segment selection value of the digital tube, so as to verify whether the input value can have the corresponding correct output. The bit width is set to 7.
(4) Used to set the driver (Sources) port, the source bit width is set to 20 (note that the picture is inconsistent), which is consistent with the bit width of the digital tube driver number
(5) Advanced setting options. Can be used to set the initial value of the drive signal and whether the send drive signal is synchronized with the source clock. (usually keep the default)
6. Click next until finish to complete the IP creation.
7. Write the top-level file and add it to the project, instantiate the nixie tube driver and ISSP IP core, as follows:
//ISSP IP 测试文件
module issp_test(
input sys_clk , //时钟信号
input sys_rst_n , //复位信号（低有效）
output [5:0] dis_sel , //数码管位选
output [6:0] dis_seg , //数码管段选
output dis_dp //数码管小数点
);
wire [3:0] num; //数码管显示的十进制数,10进制，范围0-9
//例化数码管驱动
dis_sta_dri dis_sta_dri_inst(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.num (num ),
.dis_sel (dis_sel ),
.dis_seg (dis_seg ),
.dis_dp (dis_dp )
);
//例化ISSP IP核
Sou_Pro Sou_Pro_inst (
.probe (dis_seg ), //探测数码管段选
.source (num ) //生成数码管显示数据
);
endmodule8. Fully compile the project and download the generated files to the FPGA
At this point, the creation of the IP core is completed, and then the online debugging tool is used to debug the module under test.
3. Test process and results
1. Open the online debugging tool, as follows:
2. Select your own JTAG interface on the right side of the window
3. The interface is as follows:
4. Right-click probe and source, you can select the base of the data, set probe to binary and source to decimal respectively
5. We enter 1 in the source window, and then read the detection data. The selected value of the digital tube segment read at this time is 10011111, which is consistent with the expectation.
At the same time, it is found that the digital tube on our development board shows 111111, which is consistent with the expectation
6. We enter 7 in the source window, and then read the detection data. The selected value of the digital tube segment read at this time is 00011111, which is consistent with the expectation.
At the same time, it is found that the digital tube on our development board shows 777777, which is consistent with expectations
4. Other
- It is not easy to create. If this article is helpful to you, please like, comment and bookmark more. Your support is the biggest motivation for me to keep updating!
- If you have any thoughts about this article, you can leave a message in the comment area. If you need the entire project, please leave an email in the comments or send a private message to my email (pay attention to protecting privacy).
- My own ability is insufficient, if there are mistakes, please point out a lot!
Version Information
File: V1.0
Number: 0003
Quartus II：Quartus II 13.1 (64-bit)