https://blog.csdn.net/sements/article/details/109121380
Article Directory
1-From Xilinx Zynq
2-Vitis Platform Overview
2.1-Vitis IDE
2.2-Vitis HLS / Accelerated Library
2.3-Vitis AI
2.4-Petalinux
3-The end?
The Vitis unified software platform officially launched by Xilinx can be roughly understood as making it bigger and stronger on the basis of the original SDK software, so that it can schedule other official related software, thus becoming a platform that can be accelerated for all Xilinx A unified integrated development environment for equipment (such as Alveo, ACAP, FPGA, etc.).
1-Starting from Xilinx Zynq,
traditional FPGAs only contain programmable logic, namely PL (Progarmmable Logic). Xilinx’s Zynq series embeds one or more ARM cores on a single FPGA chip. This SOC part is called PS (Processing System).
In fact, you can build a SOC directly on the PL, such as using ARM's Cortex-m3 core IP and Micro Blaze. However, compared to directly embedding a mature ARM core circuit into it, building a core with similar performance on the PL itself still takes up on-chip resources too much.
Since there are two parts that need to be programmed on a chip, PL needs to use bitstream to describe the hardware architecture, and PS needs to run a standalone or operating system (such as Linux). This involves the separate development of the two areas.
Those who are familiar with Xilinx's Spartan, Kintex, Virtex and other pure PL devices know that the verilog language can be used to program, debug and run the PL part in Xilinx's Vivado software; those who have played the Zynq series also know , After choosing to use the Zynq series chip in Vivado, you can add the PS IP core. After the hardware is exported, you can write a bare-metal program or a program that can run on the operating system in the Xilinx SDK. You can also use Petalinux to load the hardware description file to generate a Linux operating system that conforms to the current hardware.
Here we can summarize, basically, before Xilinx launched the Vitis unified software platform, a set of PS + PL FPGA program was developed, and the following software was basically used:
Vivado
SDK
Petalinux
However, as Xilinx's product line gradually expands, related software has also been iterated in an endless stream, such as SDSoc. With the acquisition of Deep Learning Technology by Xilinx, the Deep Learning Process Unit (DPU) and related kits were included in the bag. The official advancement of AI accelerated computing on FPGA has also been put into the fast lane. Thus, the Vitis unified software platform was born. One of the most eye-catching features is the official Vitis AI function. Most people who want to adopt artificial intelligence for easy deployment on FPGA can't wait to replace the current development tools with the latest Vitis. However, many people were confused by Xilinx's official description of Vitis and Vitis AI.
So, what is Vitis? What is the relationship between its related components? This article is what the author wrote while trying to make a partial summary and overview of the Vitis components while being dizzy. Due to the finiteness of energy and personal understanding, it is inevitable that there will be omissions, and I hope that you will not hesitate to enlighten me.
2-Vitis platform overview
Here is the personal summary of the relationship between the various components of the Vitis platform, which is easy to view.
From the official Vitis introduction and after the actual installation of the Vitis Core development kit, we can understand that the grand blueprint of the Vitis unified software platform mainly includes the following components:
Vitis IDE
Vitis HLS (also known as Vivado HLS)
Vitis Accelerated Library
Vivado
Vitis AI
Petalinux
XRT (Xilinx Runtime library) For
installing Vitis, you can refer to this video of UP mainly eating cat food mice
2.1-Vitis IDE After
installing the Vitis Core Development Kit, you can find the Vitis software on the desktop. It is a dispatch port of the Vitis unified software platform. Opening it actually opens the Vitis IDE software interface.
For Vitis, an important concept is Platform. Here is not just a hardware description exported by Vivado, but a broader concept. It is a comprehensive concept that includes hardware and software. On this Platform, you can do many things. Comprehensive operation. (Relationship between Platform and XSA-Community Forums)
The hardware part is easy to say, we can use Vivado to export. Using Vivado after installing Vitis, after compiling the hardware part in it, we can directly call up the Vitis IDE (this is a bit similar to how we used to call up the SDK in Vivado). You can also create a new project from the Vitis IDE and choose to use an existing platform that has been added, or choose an xsa (Xilinx Shell Archive) file exported from Vivado to create a new platform.
For the software part, we can also directly compile, compile and debug applications running on bare metal or operating system in Vitis IDE. In this way, Vitis IDE itself is actually very similar to previous SDKs.
2.2-Vitis HLS / Accelerated Library
Vitis HLS is not much different from the previous Vivado HLS. The Vitis Accelerated Library is essentially more like a collection of libraries that have been optimized by Xilinx using HLS in the past (for example, using opencv in HLS). We can still call and use these accelerated and optimized libraries in HLS.
Similar to the old SDx, you can also directly call the Vitis Accelerated Library in the Vitis IDE to accelerate the code. Refer to UG1393 or Vitis 2020.1 Software Platform Release Notes for more information.
2.3-
Although Vitis AI is called Vitis AI, it has little connection with Vitis IDE at present (at least there is currently no way to use Vitis AI directly from IDE). Vitis AI is currently in the form of a pure command line and only runs under the Linux system environment. That is to say, in order to use this function, you must install the Linux version of Vitis and ensure that you have sufficient operating resources (RAM requirements above 32GB).
As shown in the overview diagram, Vitis AI can load a solidified model selected by Xilinx and put it into the Model Zoo on Github, or load a user-defined model file. The Vitis AI tool contains several components, an AI compiler, quantizer, optimizer, and analyzer, and the final model is deployed on the Deep Learning Processing Unit (DPU) on the PL side. The PS side or the computer side for the Alevo accelerator card can be called through the Xilinx Runtime library (XRT) interface.
2.4-Petalinux
Petalinux is still the old flavor. Load the hardware file exported by vivado to build a Linux system that can run on the current PL hardware environment. For its introduction and use, you can check out my Petalinux series of articles. Is it possible to directly call petalinux to build an environment instead of manually operating it? I haven't understood this yet. . . . . But it should be supported?
3-The end?
Combined with the description in the previous chapter, the overview of the Vitis unified platform drawn earlier should be easier to understand. The essence of the birth of Vitis is to facilitate the development of Xilinx products by developers, and no longer need to jump to a certain software at a certain step as in the past. You can also take a look at the previous recommended video tutorials about mice eating cat food at station B. His video has given me a lot of help during my understanding of the pit. I would like to express my heartfelt thanks to him. Everyone who is interested in Vitis can also join his QQ group: 1146499819
Regarding DPU and Vitis AI, if we have time to study later, we should also make relevant records. However, due to the existence of a lot of interference in thesis, project and graduation project, the recorded time is also in the state of non-Schrodinger cats, and exists in the state of pigeons and non-pigeons at the same time. Maybe when the interference disappears, Machima conquers the powers, and the Durin tribe goes drunk, the collapse of the probability cloud will cause the recorded existence to become true.
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