1. The basic circuit of the minimum system
The minimum system mainly includes: main chip, clock circuit, reset circuit, power circuit, program download port, expansion interface and other components.
2. Detailed explanation of each component circuit
(1) Main chip (STM32F103VET6)
1.1 Chip start mode
1) User flash memory = Flash built into the chip.
2) SRAM = The built-in RAM area of the chip is the memory.
3) System memory = a specific area inside the chip. When the chip leaves the factory, a section of Bootloader is preset in this area, which is commonly referred to as the ISP program. No one can modify or erase the content of this area after the chip leaves the factory, that is, it is a ROM area.
There are two pins BOOT0 and BOOT1 on each STM32 chip. The level status of these two pins when the chip is reset determines which area to start executing the program after the chip is reset:
Mode 1 BOOT1=x BOOT0=0 Boot from user flash memory, this is the normal working mode.
Mode 2 BOOT1=0 BOOT0=1 Start from the system memory, the function of the program started in this mode is set by the manufacturer.
Mode 3 BOOT1=1 BOOT0=1 Boot from built-in SRAM, this mode can be used for debugging.
Under normal use conditions, mode 1 and mode 2 are mainly used, so the BOOT1 pin needs to be grounded, and the BOOT0 pin can be grounded or connected to VCC (3.3V). The connection method is shown in the figure below. Pull down to realize mode selection. The pull-down and pull-up resistors are analyzed below.
1.2 Use of pull-up resistors and pull-down resistors
(According to the UP-falling in love with semiconductor explaining video at station B)
1.2.1 The principle and function of the pull-up resistor
There are two main functions of the pull-up resistor: to improve the driving ability of the circuit and to clamp the pin voltage to a certain
value
. , the pin voltage is equal to 5V, after the external 100 ohm load is connected, the pin voltage drops to 3.8V, as shown in the figure below:
After adding a 10 ohm pull-up resistor to VCC (v), the original 3.8V output of the pin becomes For 4.2V, the voltage is raised to improve the driving ability, as shown in the figure
below: adding a pull-up resistor can realize the voltage rise because the north and south of the pin of the microcontroller are connected to two MOS tubes, and when it is required to output a high level, it is connected to VCC The MOS connected to GND is turned on, and the MOS connected to GND is cut off. When the load is not connected, the IO port is equivalent to being directly connected to VCC, and the output voltage is about 5V. After the load is connected, the equivalent circuit of the microcontroller and the load is shown in the figure below , The resistance of the MOS tube and the external resistance are equivalent to series connection. According to the series voltage division, part of the output voltage is consumed by the internal resistance, and part is provided to the external load, and the output voltage is less than 5V.
After adding the pull-up resistor, the equivalent circuit is shown in the figure below. At this time, the internal resistance and the pull-up resistor are equivalent to parallel connection, and the resistance of the upper part becomes smaller. According to the series voltage division, the internal resistance of the lower part will be allocated to a higher voltage. When the voltage is raised, the driving capability of the IO port will also be improved. This is the principle of the pull-up resistor improving the driving capability.
Another function of the pull-up resistor is to clamp the potential. When the IO of the microcontroller is in the open-drain output, the upper MOS tube is cut off, which is equivalent to connecting an infinite resistance. To achieve high-level output, the lower MOS tube must also be in the cut-off state. , At this time, two MOS tubes can be equivalent to two infinite resistors, and the circuit output is in an uncertain state, as shown in the figure below: At this time,
we connect an external 10K pull-up resistor, and the pull-up resistor is connected in parallel with the internal upper resistor , the equivalent maximum reduction. According to the principle of series voltage division, the lower resistance is infinite, and the power supply voltage is almost all added to this resistance. When we measure the external voltage, the output voltage is approximately equal to 5V, and the potential clamping effect is realized. In short, the upper The principle of the pull resistor is to connect it in parallel with the internal resistance, reduce the equivalent resistance, distribute more voltage to the load, and achieve voltage rise or potential clamping.
1.2.2 The principle and function of the pull-down resistor
The pull-down resistor is connected between the input pin of the MCU and GND. As shown in the figure below,
a digital input pin of the MCU and a serial port are used for simulation. The input pin is not connected to peripherals. When the pin is high, the serial port outputs 1. When the pin is at low level, the serial port outputs 0. The experimental results show that the input state of the input IO port has been changing and is in an uncertain state.
After the input pin is connected to the pull-down resistor, the experimental results are shown in the figure below. The input of the microcontroller remains in a low state, so the pull-down resistor can clamp the level of the input pin to a specific state. Why can the pull-down resistor realize the potential What about clamping? 
After simplifying the input pin of the microcontroller, the equivalent circuit can be obtained as shown in the figure below. After adding the pull-down resistor, the internal triode is cut off. There is a large resistance between different regions, and the external resistance is much smaller than the internal resistance. Therefore The internal VCC voltage is still applied to the internal triode. From the IO voltage to 0, the pull-down resistor clamps the unit at 0V. There is a problem here, why can’t the IO port be directly connected to GND, which can also save a resistor? The reason is that after directly connecting the IO to GND, when the IO enters and exits the high-level input, the current directly passes through the GND and will not flow into the IO, so that there is no way to collect the external input signal, so a pull-down resistor must be added. The pull-down resistor is in When there is no IO input, ensure that the IO level is low, and when there is input, the IO can normally collect the input signal.
1.3 Main chip power supply
1.3.1 Decoupling Capacitors
According to the data sheet of the chip, an external decoupling capacitor is required between the chip power interfaces of STM32. Assuming that there are n VSS and VDD, you need to choose n 100nf and 1 4.7uf capacitors as decoupling capacitors. In our abbreviation There are 5 VDD/VSS on the STM32F103ZET6 chip, so choose 5 100nf capacitors and a 4.7uf capacitor. The schematic diagram is shown in the figure below. The
decoupling capacitor should be placed as close to the chip as possible when wiring the PCB, and evenly distributed Around the power supply pins of the chip, the capacitance values are arranged outward in order from small to large. When installing decoupling capacitors, holes are drilled on both sides of the pad to connect to the power plane and ground plane.
In addition, in addition to the need to supply power to the power supply, it is also necessary to provide a reference voltage for the ADC. According to the manual, VREF+ and VREF- need to be provided. Among them, VREF- can be directly connected to the VSS of the power supply. VREF+ can provide VREF as a reference voltage or use the power supply. VDD is used as the reference voltage, and a 100nf and a 1uf filter capacitor need to be connected between the reference voltages. The schematic diagram is shown in the figure below.
(2) Reset circuit
According to the official data sheet, the reset pin of the chip is connected to the internal permanent pull-up resistor, that is, the default is high level, and the chip will reset when we provide a low level. Reset low level reset (-0.5——0.8) V, high level is (2——VDD+0.8) V, and connect to power supply VCC and GND by default.
The reset circuit is shown in the figure below. It is at high level in the default state, and it is connected to GND after pressing the button. The function of capacitor C9 is to realize the debounce of the button.
(3) Crystal oscillator circuit
3.1 Crystal selection
The external clock of STM32 mainly consists of two parts: external high-speed clock and external low-speed clock.
The frequency of the external high-speed clock is typically 8MHz, which is convenient for generating a clock frequency of 72Mhz. The specific selection range and the high and low level range of the clock pin are provided in the data sheet, as shown in the figure below.
The external four-degree clock uses 32.768KHz. According to the data sheet, the maximum value is less than 1KHz. The purpose of choosing 32.768KHz is that 32.768K is equal to the fifteenth power of 2, that is, 32.768KHz can be obtained after fifteen times of frequency division by two. 1Hz, convenient to use. The specific selection range is shown in the figure below.
3.2 Construction of crystal oscillator peripheral circuit
3.2.1 External circuit of high-speed crystal oscillator
The 8MHz crystal oscillator circuit is shown in the figure below. The crystal oscillator needs two external capacitors. The choice of the two capacitors is not random. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors, and the range of 5pf to 25pf is recommended. CL1 and CL2 are usually the same size, and the load capacitance usually specified by the crystal manufacturer is the parallel capacitance of CL1 and CL2. When determining the load capacitance, the PCB and MCU pin capacitance must be included, and 10pf can be used as a rough estimate for the combined pin and board capacitance.
3.2.2 External circuit of low-speed crystal oscillator
The application circuit of the 32.768KHz low-speed crystal oscillator is shown in the figure below. Two capacitors are also required. It is recommended to use 5-15pf ceramic capacitors for the two capacitors. The large specifications of the two capacitors are the same. The specific capacitance value can be determined according to the competing load capacitance Under normal circumstances, the calculation formula of the competitive load capacitance is CL = CL1 x CL2 / (CL1 + CL2) + Cstray, where Cstray is related to the pcb trace of the circuit, generally about 2-7pf, The calculation formula of the load capacitance is also applicable to the calculation of the load capacitance of the high-speed crystal oscillator. If there is no precise frequency requirement, download and select a value within the recommended range. When choosing a crystal oscillator, try to use a crystal oscillator with a load capacitance lower than 7pf. It is not recommended to use a crystal oscillator with a load capacitance of 12.5pf.
3.2.3 Circuit design
High-speed crystal oscillator circuit:
load capacitance CL=20pf
is calculated by: CL = CL1 x CL2 / (CL1 + CL2) + Cstray (10pf), and CL1=CL2=20pf is calculated, which is within the official recommended range.
Low-speed crystal oscillator circuit: It is used for not having high requirements on the accuracy of the clock, so a 20pf capacitor is selected to save costs. The schematic diagram is shown in the figure below.
(4) Power circuit
As mentioned in the previous chapters, the power supply required by the single chip microcomputer is 3.3V, and most of the external power supply is 5V or 12V, so the input voltage needs to be stepped down, and the voltage regulator chip packaged by ME6206A33-ST023 of Weimob Electronics is selected. The specific parameters and application circuit are shown in the figure below.
(5) Download circuit
In order to facilitate downloading and debugging, two methods of SWD downloading and USB downloading are designed. The USB
downloading circuit chooses to use the CH340N chip. The D-data interface of the USB bus does not need a series resistor; VCC: power input, an external 100nf decoupling capacitor is required; GND: power input GND; V3: the power supply is 5V input, an external 100nf decoupling capacitor is required and then grounded; RDX: : Data input, connected to the TX of the MCU; TXD: Data output, connected to the RX of the MCU; 16PIN Type-C interface, the pin function diagram is shown in the following figure:
The schematic diagram of the circuit is as follows:
The SWDIO download circuit is shown in the following diagram:
(6) Expansion interface
Power supply indicator The design of
the extended IO
schematic diagram is over. I don’t know if it can be realized, but wiring, PCB proofing, and testing are still needed.
After several days of waiting, the board has arrived. After actual testing, the board is fine!
(Before this, I used other people's schematic diagrams. I didn't know the principle. This time I spent it myself according to the data manual. If there are any deficiencies, I hope you can criticize and correct me. I am happy to continue to improve my minimal system!!)
