The basic principles of FSMC have been explained in these two articles. If there is any suggestion that you do not understand, please read it first. Here we will talk less about some basic concepts, mainly focusing on the characteristics of FMC and the difference between FSMC and FMC. Explanation (not much difference).
STM32 FSMC/FMC principle nanny level explanation (1)
STM32 FSMC/FMC principle nanny level explanation (2)
Detailed explanation of the concepts of SDRAM, DRAM and DDR FLASH ROM
Difference between FSMC and FMC
F1 and F407 are exclusive FSMC（Flexible static memory controller）“静态存储器控制器”to Cortex-M3内核the chip, and STM32 can be connected to the pins of static SRAM, ROM, PSRAM, Nor Flash and NandFlash memory through FSMC to exchange data.
In Cortex-M4内核the F429 and Cortex-M7内核F7, H7 series, it has become FMC(Flexible Memory Controller) 灵活存储控制器, supports dynamic SDRAM and other devices,
What is the biggest difference?
FMC is a bus controller that extends SDRAM on the basis of FSMC (Flexible Static Memory Controller). Using FMC, SDRAM can be dynamically refreshed.
Static RAM and Dynamic RAM
SRAM
SRAM, static random access memory, also known as static RAM, uses bistable circuits for storage. Even if there is interference, it has no effect on the steady-state circuit, so there is bistable. "Static" means that as long as the power is not turned off, the data stored in the SRAM can always be saved . As long as there is power, the data in the SRAM will not be no change. In the case of power-on, there is no need to refresh all the time, data will not be lost, and,
DRAM
DRAM, dynamic random access memory, requires constant refreshes to preserve data . The main principle of action is to use the amount of stored charge in the capacitor to represent whether a binary bit (bit) is 1 or 0. In reality, the capacitor will leak current, resulting in insufficient potential difference and the memory will disappear. Therefore, unless the capacitor is regularly charged, the memory cannot be guaranteed for a long time. DRAM reads are destructive, that is, the data in a row of memory cells is destroyed during a read operation. Therefore, the row data must be written back into the same row at the end of a read or write operation on that row. This operation is called precharge and is the last operation on the line. This operation must be completed before a new row can be accessed, which is called closing an open row.
SDRAM (Synchronous Dynamic Random Access Memory), synchronous dynamic random access memory. synchronous DRAM
The difference between synchronous and asynchronous is that the synchronous method requires a dedicated off-chip clock CLK signal pin, and all read and write operations follow this clock signal.
Summary of the difference between FSMC and FMC
FSMC can only be connected to static SRAM, FMC can be connected to dynamic DRAM, and controlling dynamic DRAM is much more complicated. Dynamic RAM needs to be refreshed periodically, otherwise the data in RAM will be lost,
This creates a "management" problem. If you read the FSMC principle above, you will know that data is only read and written between the memory and STM32.
If an MCU is used to connect the DRAM, the exchange between the two is not only as simple as data exchange, but also includes control information. Periodically refresh the data in the DRAM, so that in addition to the data storage unit in the DRAM, there are also registers and an "initialization" process for the DRAM.
So complicated, some students will ask why use DRAM? Can't you just use SRAM?
If you read the difference between DRAM and SRAM above, you will know that the capacity of SRAM is smaller than that of DRAM, and the price is much higher than that of DRAM, so SRAM is generally only used for storage inside the CPU, while the external gigabytes on our computer The memory sticks are of the dynamic DRAM type.
Introduction to FMC
Let's take a look at the official introduction to FMC:
FMC flexible storage controller. FMC can be connected to SRAM (asynchronous or synchronous), SDRAM, NORFLASH, PC card, NANDFLASH. Support burst mode, programmable clock, 8-bit, 16-bit, 32-bit wide data bus. FMC has 6 storage areas, each area supports 256MB of addressing space.
Features of FMC:
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A major feature of FMC is that it supports asynchronous read and write operations of different bit widths.
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FMC can only control one memory peripheral at the same time (because the address line, data line and control line configured by fmc are shared); each memory area has its own bank chip select signal;
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FMC contains three types of memory controllers: NOR/PSRAM/SRAM memory controller, NAND controller, and SDRAM controller;
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Any unused pins in the FMC configuration can continue to be used as general-purpose I/O modes or other multiplexing functions, as long as the FMC multiplexing is not configured.
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The memory space configuration under each chip selection is independent, with special registers, which do not affect each other
Parallel bus interface FMC
FMC (Flexible memory controller, flexible dynamic memory)
The principle block diagram of FMC in H7 is shown in the following figure:
1.
On the right side of the block diagram are the control pins related to the FMC peripheral, where the address line FMC_A and the data line FMC_D are shared by all controllers. The FMC_NBL data mask is shared by SRAM.
The specific GPIO ports and pin numbers corresponding to the different memory pins of the FMC can be found in the "STM32H7xx Specifications" and are not listed here. For SDRAM controller, the following FMC and SDRAM pin correspondence
Address Mapping of FMC
2.
The left side of the figure is the memory space allocation of the Cortex-M7 core, and the right side is the address mapping of the STM32 FMC peripherals. It can be seen that
the addresses of FMC's NOR/PSRAM/SRAM/NAND FLASH and PC card are in the External RAM address space, while the
SDRAM address is allocated to the External device area. It is precisely because of such an address mapping that accessing
the memory controlled by the FMC is the same as accessing the on-chip peripheral registers of the STM32 (the address mapping of the on-chip peripherals is the
"Peripheral" area on the left side of the figure).
FMC can be divided into 6 areas, each sub-area has its own connected memory type
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The first area is used for NORFLASH, PSRAM, SRAM and can be divided into 4 sub-areas, each sub-area has its own chip select signal, which can be connected to 4 devices
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Areas 2 and 3 are used for NAND Flash, each area can only connect 1 device
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Area 4 is used to connect PC cards
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Areas 5 and 6 are for SDRAM, only 1 device can be connected to each area
FMC remapping
Different from F1 and F4, the FMC bus interface of H7 series supports remapping, that is, the location of these pieces of memory can be set.
According to the value 00, 01 or 10 set by BMAP[0:1], three allocation methods are supported. By default, the allocation method of BMAP[0:1] = 00
can be used, which is the allocation method in the screenshot above.
FMC clock
3.
The FMC peripheral is mounted on the AHB3 bus, the clock signal comes from HCLK (default 200MHz), and the clock output of the controller is
obtained by dividing it. You can also choose the following clock sources HCLK3, PLL1Q, PLL2R and PER_CK
We use HCLK3 directly here. When the main frequency of STM32H7 is configured to be 400MHz, the output of HCLK3 is 200MHz, which is the highest clock supported by FMC.
In SDRAM, the FMC_SDCLK pin of the SDRAM controller outputs the clock frequency for
synchronous communication with the SDRAM chip. Its clock frequency can be configured through the SDCLK bit in the FMC_SDCR1 register, and can be configured as
1/2 or 1/3 of the HCLK. , that is to say, the maximum frequency of the synchronous clock for communication with SDRAM is 100MHz.
NOR/PSRAM/SRAM block.
This block is used the most. For example, the NAND and SDRAM blocks can only be connected to NAND and SDRAM, while the NOR/PSRAM/SRAM area is different. In addition to these types of memories, you can also connect to TFTLCD, OLED , AD7606 and other bus peripherals. This block has 4 chip selects, namely FMC_NE1, FMC_NE2, FMC_NE3 and FMC_NE4. These chip selects have corresponding pins on the chip. Each chip select can manage 64MB of access space, which is derived from FMC. Determined by the 26-way address line FMC_A[0:25], 2^26 = 64MB.
FMC_NE1: The first address is 0x6000 0000, and the address range that can be managed is 0x6000 0000 to 0x63FF FFFF.
FMC_NE2: The first address is 0x6400 0000, and the address range that can be managed is 0x6400 0000 to 0x67FF FFFF.
FMC_NE3: The first address is 0x6800 0000, and the address range that can be managed is 0x6800 0000 to 0x6BFF FFFF.
FMC_NE4: The first address is 0x6C00 0000, and the address range that can be managed is 0x6C00 0000 to 0x6FFF FFFF.
STM32 FSMC/FMC principle nanny level explanation (1)
This part we have explained in this article in great detail, if you don't understand, please read it again
Here we talk about the storage configuration of SDRAM
Through the FMC address block diagram, we can see that STM32 allocates two bank spaces Bank1 and Bank2 for SDRAM . The Bank here is different from the Bank inside the SDRAM chip. This means that there are two physical Bank addresses inside the FMC. Each BANK can be connected to one SDRAM. It can be understood that FMC supports connecting 2 SDRAM chips. When actually using it, see whether the specific wiring selection is BANK1 or BANK2.
The MCU selects which off-chip RAM to use through different chip select signals SDNE0 and SDNE1, and determines which BANK clock is enabled through SDCKE0 and SDCKE1
The address range of storage area 1 corresponding to BANK0 is 0xC000 0000-0xCFFF FFFF,
and the address range of storage area 2 corresponding to BANK1 is 0xD000 0000-0xDFFF FFFF.
When the control kernel accesses the memory space of these addresses in the program, the FMC peripheral will generate the corresponding timing to read and write to its external SDRAM chip.
