I'm a little dizzy when I'm doing a project recently, and I didn't learn the matrix well to revenge me.
I have seen the technical requirements for FPGA developers at different levels before, so I decided to open a new series to explain the necessary skills of FPGA engineers from simple to difficult.
Phase 1: Digital Circuit Stability
The reason for the instability of digital circuits is ultimately caused by " the transmission rate of the signal is not ideal ": due to various effects of temperature, process, path, and logic gates, the transmission rate is not ideal, so certain These signals are still low when we want it to be high, or vice versa, which will affect the output of the digital circuit.
We call the situation where the signal arrives at the port at a different time as " competition ", and call the phenomenon of output errors it produces as " risk ". Competition can cause risks !
The output signal caused by the error generally appears as a high-frequency sharp pulse signal in electrical characteristics, so we call it a glitch
. We often see glitches in combined sequential circuits and asynchronous sequential circuits.
① Let me talk about the combinational logic circuit first:
Take the AND gate as an example. For example, if we set a time axis t, the initial states of A and B are both 0. According to my design, A and B should be flipped to 1 at the same time in 5ns, so Y should also be in Turns over from 0 to 1 at t=5ns. However, due to the difference between A and B signal sources, A is 2ns ahead of B, then our high level start time will change, and the duration will also change.
So how do we eliminate glitches in combinational logic circuits?
In the course of digital electronics, we may have talked about:
1. Add redundant items 2. Increase capacitance
at the output terminal. First of all, these two methods, one is that the redundant item can only eliminate the logic hazard, but not the function hazard, and the second , Increasing the capacitance will cause the system to slow down. Moreover, in FPGA design, these two methods are obviously not feasible, so we want to introduce another method:
Gating method:
That is, adding additional strobe pulses, using the digital switch realized by the AND gate structure to manage input or output signals, so that the generation of burrs is prevented from the source.
②Then talk about the glitch in the asynchronous sequential circuit:
Cause: If multiple status registers change at the same time , then the sequential circuit is already in competition, and when the final steady state of the circuit is related to the sequence of status register changes , then there is already competition at this time.
Solution:
1. Delay component method: directly delay a certain status register to achieve the output we want. This method does not directly solve the glitch problem, but only uses competition.
2. Multiple transfer method: If there is competition in A->D, then we can try A->C->D (at this time, there is no competition and risk in the two steps)
3. Transform into a synchronous circuit: After just two methods , You may understand: Asynchronous circuits can't eliminate glitches in the true sense. They can only be transformed into synchronous circuits to deal with glitch problems. Synchronous timing in ASIC occupies a larger area than asynchronous timing, but in FPGA, circuit area means logic unit. In this case, the resources of synchronous and asynchronous circuits are similar, and it will not cause unbearable waste.
This is the end of the introduction, thank you for watching.