When using Modelsim to simulate Verilog code, Modelsim automatically optimizes the waveform that cannot be generated
The following simulation information:
vsim work.SDRAM_interface_tb
# vsim
# Start time: 14:57:38 on Mar 28,2020
# ** Note: (vsim-8009) Loading existing optimized design _opt
#
# Loading work.SDRAM_interface_tb(fast)
Then just stuck here.
Solution:
- Enter the following script in the Transcript command window in Modelsim to cancel the optimization:
vsim work.顶层模块名 -novopt 或者 vsim -novopt 顶层模块名
Uncheck Enable optimization under Modelsim software->Simulate->Start Simulation and click OK to start the simulation.