Introduction to Core Board
Chuanglong SOM-TL6678 is a high-end multi-core DSP industrial-grade core board based on TI’s KeyStone architecture C6000 series TMS320C6678 octa-core C66x fixed-point/floating-point high-performance processor. The processor core frequency can be as high as 1.25GHz. The connector leads to high-speed communication interfaces such as Gigabit Ethernet, SRIO, PCIe, HyperLink, and EMIF16. The core board has been verified by professional PCB Layout and high and low temperature testing, which is stable and reliable and can meet various industrial application environments.
When users use the core board for secondary development, they only need to focus on the upper-level application, which reduces the development difficulty and time cost, and can quickly conduct product plan evaluation and technical pre-research.
Figure 1 Front view of the core board
Figure 2 The back view of the core board
Typical should use field
- Software radio
- Radar detection
- Photodetection
- Video tracking
- Image Processing
- Underwater detection
- Positioning navigation
Software and hardware parameters
Hardware block diagram
Figure 3 The core board hardware block diagram
Figure 4 TMS320C6678 processor functional block diagram
Hardware parameters
Table 1
| CPU |
CPU ： TI C6000 TMS320C6678 |
| 8x TMS320C66x fixed-point/floating-point DSP core, clocked at 1/1.25GHz |
|
| 1x Network Coprocessor |
|
| ROM |
128MByte NAND FLASH |
| 128Mbit SPI NOR FLASH |
|
| 1Mbit EEPROM |
|
| RAM |
1/2GByte DDR3 |
| ETC |
256/512MByte DDR3 |
| SENSOR |
1x TMP102AIDRLT temperature sensor |
| LED |
1x power indicator |
| 2x user programmable indicator lights |
|
| B2B Connector |
2x 50pin male B2B connector, 2x 50pin female B2B connector, pitch 0.8mm, height 5.0mm; 1x 80pin high-speed B2B connector, pitch 0.5mm, height 5.0mm; Total 280pin |
| Hardware resources |
1x SRIO, four ports, four channels in total, each channel has a maximum communication rate of 5GBaud |
| 1x PCIe Gen2, a dual-channel port, each channel has a maximum communication rate of 5GBaud |
|
| 2x Ethernet，10/100/1000M |
|
| 1x EMIF16 |
|
| 1x HyperLink |
|
| 2x TSIP |
|
| 1x UART |
|
| 1x I2C |
|
| 1x SPI |
|
| 1x JTAG |
Software parameters
Table 2
| DSP end software support |
SYS/BIOS operating system |
| CCS version number |
CCS5.5 |
| Software development kit provided |
MCSDK |
Development Information
- Provide core board pin definition, editable bottom board schematic diagram, editable bottom board PCB, chip datasheet, shorten the hardware design cycle;
- Provide a complete platform development kit, introductory tutorial, save time for software organization, easy to get started;
- Provide a wealth of Demo programs, including multi-core DSP architecture communication tutorials, which perfectly solve the bottleneck of multi-core development.
Development routines mainly include:
- Development routines based on SYS/BIOS
- Multi-core development routines based on IPC and OpenMP
- SRIO, PCIe, EMIF16 development routines
- DSP algorithm development routine
Electrical characteristics
working environment
table 3
| Environmental parameters |
Minimum |
Typical value |
Max |
| Working temperature |
-40°C |
/ |
85°C |
| Operating Voltage |
/ |
9V |
/ |
Power consumption test
Table 4
| category |
Typical voltage |
Typical current |
Typical power consumption |
| Core board |
9.17V |
961.6mA |
8.82W |
Note: The power consumption is measured based on the TL6678-EasyEVM evaluation board. The power consumption test data is related to specific application scenarios, and the test data is for reference only.
Mechanical Dimensions
table 5
| PCB size |
80mm*58mm |
| PCB layers |
12 floors |
| Plate thickness |
1.6mm |
| Number of mounting holes |
6 |
Figure 5 Mechanical dimensions of the core board (top perspective view)