Introduction to the high-performance ARM SOC core board standard (SMARC2.1)

     The high-performance Arm processor system generally adopts the core board mode. The core components such as the processor and memory are deployed on a small-size PCB, and the IO signals are led out through golden fingers or high-density connectors. There are also postage stamps. This structure greatly simplifies the design and manufacturing difficulty of high-performance computing equipment. And it brings flexibility to the rapid development of application equipment.

This structure is also called Computer-On-Modules (COMs). In the early stages of development, this kind of module was not standardized, and each manufacturer had its own business. The Standardization Organization for Embedded Technologies (SGET) has proposed a standard called SMARC ("Smart Mobility ARChitecture"), and version 2.1 was released in May 2020.

SGET's official website ( https://sget.org/standards/smarc/ )

 

SMARC ("Smart Mobile Architecture") is a general definition of small computer modules whose target applications are applications requiring low power consumption, low cost and high performance. These modules usually use ARM SOCs that are similar or identical to those used in many familiar devices (such as tablets and smartphones). Other low-power SOCs and CPUs can also be used, such as X86 devices for tablet PCs and other RISC CPUs. The power of the module is usually less than 6W.

The standard defines two module sizes: 82mm x 50mm and 82mm x 80mm. There are 314 golden fingers on the module PCB, which can be connected to a 314-pin memory strip socket with 0.5mm pitch.

At present, many companies have introduced the Arm core module that composes SMARC2.0/2.1 standards.

 

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Origin blog.csdn.net/yaojiawan/article/details/108470723