Static library writing:
Write the .o file gcc -c ( lowercase) seqlist.c (need to be in the same file directory as the header file and main.c file)
libs.a-> Remove lib and .a and the rest is the name of the library 's'.
-ls means the library name is s.
-L The path to the library.
Makefile file writing:
CFLAGS=-Wall -O2 -g -I ./inc/
LDFLAGS=-L./lib/ -llist
APP=app
SRC=$(wildcard ./src/*.c)
OBJ=$(patsubst %.c, %.o, $(SRC))
CC=gcc
$(APP):$(OBJ)
$(CC) -o $(APP) $^ $(LDFLAGS)
clean:
rm -f $(OBJ) $(APP)
This is the compiled file, and the app file is the compiled binary file.
The relationship between makefile and shell script
Shell scripts and makefiles are two completely different tools, but they are often used together on UNIX and Linux systems, especially in software building and automation toolchains. Let's look at them individually and then explore how they are related.
1. Shell script:
- Shell script is a scripting language for automation, which can be run in Unix or Linux shell.
- It is typically used to perform day-to-day file and directory operations, process text, and perform system administration tasks.
- Shell scripts can be run directly on the command line, or saved as .sh files and executed as scripts.
2. Makefile:
-makefile is a file used by the make tool, which describes how to build a target (usually an executable program or library) from source code.
- It contains a set of rules that define object files, dependencies, and instructions for converting dependencies into targets.
- Directives are usually shell commands, so makefiles frequently use shell scripts.
- The `make` tool checks the timestamps of files to determine which files need to be updated, so that only those parts that actually need to be updated are built instead of building the entire project from scratch.
Relationships:
- In makefiles, you will often see shell commands. This is because make uses shell commands to perform build tasks.
- `make` can execute any command that can be run in the shell, including calling shell scripts.
- Typically, smaller tasks (such as compiling a single file) are done directly in the makefile using shell commands, while more complex tasks (such as deploying an application) may invoke separate shell scripts.
- In short, makefiles usually invoke shell commands (or other tools, such as compilers) to do their work. Therefore, shell scripts and makefiles are often used together during the build and deployment process.
In real development, especially in large projects, using make and makefiles can greatly simplify the build process, while shell scripts provide additional flexibility and power for automation.