OLED concept introduction

1. OLED concept:

• Introduction

OLED, that is, organic light-emitting diode.

OLED has self-illumination, no backlight and high contrast.

LCDs all require backlighting, while OLEDs do not, because it is self-luminous. In this same display, the OLED effect is better. With the current technology, the size of OLED is still difficult to enlarge, but the resolution can be very high.

The OLED controller is SSD1309.

 

• In kind

 

 

Second, OLED controller SSD1309

General instructions:   

SSD1309 is a monolithic CMOS OLED / PLED driver chip that can drive an organic / polymer light-emitting diode dot-matrix graphic display system. Consists of 128 segments and 64 Commons. The chip is specifically designed for common cathode OLED panels. 

SSD1309 has embedded contrast controller, display RAM and crystal oscillator, and thus reduces external devices and power consumption. There are 256 levels of brightness control. There are three kinds of interfaces for sending data / commands: 6800/8000 serial port, I2C interface or SPI interface.

It is suitable for most introductory applications, such as mobile phone screen display, MP3 player and calculator. 

• interface

    The MCU (STM32 / C51) can send data or commands to the SSD1309 through the hardware data interface (SPI / IIC / 8080/6800).

• SSD1309 interface mode, there are multiple interface modes:

1. 6800 series interface   

2. 8080 series interface  

3. MCU serial interface (4-wire SPI)   

4. MCU serial interface (3-wire SPI)   

5. MCU I 2 C interface 

Choice of interface:

The SSD1306 MCU interface consists of 8 data pins and 5 control pins. Pin assignment is determined by different interface options,

The details are as follows. Different MCU modules can be set by hardware selection of BS [2: 0] pins. 

Generally use 4-wire SPI.

Features:

characteristic 

1. Resolution: 128 * 64 dot matrix panel 

2. Power supply: 

            a) VDD = 1.65V to 3.3V for IC logic 

            b) VCC = 7V to 15V for panel drive  

3. Dot matrix display 

            a) OLED drive output voltage, maximum 15V 

            b) Segment maximum current: 100uA 

            c) Common maximum reverse current: 15mA 

            d) 256-level contrast brightness current control 

4. Embedded 128 * 64 bit SRAM display cache 

5. Pin selection MCU interface (there is a pin selection on the back of the display, different interfaces are selected by welding different resistors)

           a) 8-bit 6800/8000 serial port 

           b) 3/4 wire SPI interface 

           c) I2C interface 

6. The screen saves continuous scrolling in both horizontal and vertical directions. 

7. RAM write synchronization signal 

8. Programmable frame rate and multiple ratio 

9. Row remapping and column flush mapping 

10. On-chip crystal 

11. Two packages COG and COF 

12. Wide operating temperature range: -40 ℃ to 85 ℃ 

 

Block diagram

 

Timing and pin introduction

4-wire SPI timing

The 4-wire serial interface includes serial clock: SCLK, serial data: SDIN, D / C #, CS #. In 4-wire SPI mode, D0 acts as SCLK and D1 acts as SDIN. For unused data pins, D2 should be left open. From pins D3 to D7, E and R / W # (WR #) # can be connected to external ground.

 

Note 

(1)

 H stands for HIGH in signal 

(2) 

L stands for LOW in signal 

(3)

 ↑ stands for rising edge of signal 

 

On each rising edge of SCLK, SDIN is shifted into the 8-bit shift register in the order of D7, D6, ... D0. D / C # samples every eight clocks and writes the data bytes in the shift register to the graphic display data RAM (GDDRAM) or command register in the same clock.

In serial mode, only write operations are allowed.

Figure 8-5: Writing process in 4-wire serial interface mode

Command decoder (D / C # pin)

This module determines whether input data is interpreted as data or commands. The data is based on interpretation on the input of the D / C # pin.

 If the D / C # pin is high, D [7: 0] is interpreted as the display data written to the image display data RAM (GDDRAM).  

If it is low, the input of D [7: 0] is interpreted as a command. Then the data input will be decoded and written to the relevant command register. 

 

Restart the circuit (RES #)  

 

When the RES # input is LOW, the chip initializes to the following state: 

1. Display off 

2. 128 * 64 display mode 

3. Normal segment and display data column address and row address mapping (SEG0 maps to address 00h, COM0 maps to address 00h) 

4. Clear the shift register data in the serial port 

5. The display start line is set to display RAM address 0 

6. Set the column address count to 0 

7. Normal scan COM output direction 

8. The contrast control register is set to 7Fh 

9. Normal display mode (equivalent to A4h command) 

  Video memory

The total memory of SSD1309 is 128 * 64bit,

Graphical display data RAM (GDDRAM) GDDRAM is a bit pattern for mapping static RAM to display. The size of the RAM is 128 * 64 bit, the RAM is divided into 8 pages, from PAFE0 to PAGE7, for monochrome 128 * 64 dot matrix display, as shown below 

Common command table

Omitted. . .

Set memory address mode (20h) 

There are three different memory address modes in SSD1306: page address mode, horizontal address mode, and vertical address mode. This command sets the memory address mode to one of these three.

• Page address mode (A [1: 0] = 10xb) 

In page address mode, the column address pointer is automatically incremented by one after the display RAM is read and written. If the column address pointer reaches the end address of the column, the column address pointer is reset to the column start address and also the address pointer does not change. The user needs to set a new page and column address to access the RAM in the next page. Refer to the figure below for the movement mode of PAGE and column address pointers in page address mode 

In the normal display data RAM read or write and page address mode, the following steps are required to define the location to start RAM access: 

1. Set the page start address of the target display position by commands B0h to B7h 

2. Use 00h ~ 0Fh to set the pointer of the low start column address 

3. Use command 10h ~ 1Fh to set the high start column address 

 

• Horizontal addressing mode (A [1: 0] = 00b) 

In the horizontal addressing mode, when the display RAM is read and written, the column address pointer is automatically incremented by one. If the column address pointer reaches the end address of the column, the column address pointer is reset to the start address of the column, and the page address pointer is automatically incremented by one. The moving order of page and column addresses in horizontal addressing mode is shown in the figure below. When both the column address and the page address have reached the end address, the pointer is reset to the start address of the column address and the page address.

• Vertical addressing mode (A [1: 0] = 01b) 

In vertical addressing mode, when the display RAM is read and written, the page address pointer is automatically incremented by one. If the page address reaches the end address of the page, the page address is automatically reset to the start address of the page, and the column address is automatically incremented by one. The moving order of page address and column address is shown in the figure below. When both the column address and the page address reach the end address, the pointer is automatically reset to the start address. 

 

Under normal display RAM read or write, horizontal / vertical addressing mode, the following steps are required to define the RAM access pointer location: 

1. Use the 21h command to set the start and end addresses of the target display position column;

2. Use command 22h to set the start and end addresses of the page at the target display position