Why don't the asynchronous clock set false path
For beginners, it is often believed that the asynchronous circuit should be set to false path. Even many veterans think so.
In fact, for asynchronous circuits, there are special sdc commands to complete this task.
set_clock_groups -asynchronous
In terms of function, it seems to have the same effect as the false path. So why is there such a command.
Imagine that there are two clocks, clka and clkb, which belong to an asynchronous relationship. How should they be set?
Using the clock group method:
set_clock_groups -group clka -group clkb 【命令1】
Use the false path method:
set_false_path -from [get_clock clka] -to [get_clock clkb] 【命令2】set_false_path -from [get_clock clkb] -to [get_clock clka]
In comparison, it seems that the clock group method is more intuitive, but the difference is not big.
So what is the real reason for designing this asynchronous command? What is the fundamental difference between it and the role of false path?
In the manual of set_false_path, there is such a sentence that explains the real difference between the two:
To sum up, if you want to use asynchronous circuits, you must use command 1. If you use synchronous circuits, you must use command 2. The calculation methods for crosstalk are different.
I have encountered this problem in the project once, and should have set the false path in the case of asynchronous. Since this problem was discovered after timing clean, it is easy to compare the differences between the two after modification.
The result is that after changing to the setting of command 1, timing becomes worse, and some paths even have hundreds of ps.
If you are interested, you can experiment with your own design, there may be surprises.
So what is the difference between the crosstalk analysis mentioned in the manual?
As shown in the figure, in crosstalk analysis, when the transition of signal A and signal B occurs at the same time, then signal B will have a delta delay due to the influence of signal A. If the transition of signal A is too early or too late, then there is no effect on the delay of signal B.
So when is the two nets aggressor and when is the victim? It depends on which net we are analyzing. Since we are analyzing the effect of signal A on signal B, signal A here is the aggressor and signal B is the victim. vice versa. Generally, there is more than one aggressor for a victim in the actual design. Similarly, for an aggressor, there will be more than one victim.
When performing on-chip-variation mode analysis. Every aggressor and victim jump will have an earliest arrival time and a latest arrival time. This window between the earliest and latest arrival time is called timing window. Only when the timing window of the aggressor and victim overlap, the delta delay will be generated, that is to say, the aggressor will affect the victim.
If set false path, the tool will continue to calculate the timing window according to the synchronization relationship.
And we know that for the case where agressor and victim belong to two clocks with an asynchronous relationship, the aggressor's transition may occur at any time during the entire clock cycle of the victim. Not just in the timing windlow calculated according to the synchronous clock.
According to the synchronization relationship, the impact of the aggressor on the jump outside the timing window of the victim is ignored by the tool. This may cause serious consequences, ranging from performance degradation (setup) to chip failure (hold)
In short, set the false path carefully, and strive for a chip success.