The clock is the reference of all signals in the digital circuit, especially in the FPGA, the clock is the power, the blood, and the core of the sequential circuit. There is no clock or the clock signal is not handled properly, which will affect the performance and even the function of the system. Therefore, in general, the same clock source is used in the same design. When there are multiple clocks in the system, different clocks need to be selected according to different situations. The processing method is to synchronize all the clocks. The following describes the synchronization processing methods of the clocks in several cases.
The first case:
When there are multiple clocks in the same digital circuit, and the rate of one clock (Clk) is more than twice that of the other clocks.
This situation is the simplest. In the interface part, other clocks must be synchronized and processed as a clock signal synchronized with Clk.
The benefits of doing this are:
It is convenient to deal with the internal timing of the circuit;
The boundary conditions between clocks are only handled in the interface circuit.
In essence, the synchronous processing method of clock sampling is the rising edge extraction circuit. The output information extracted by the rising edge contains the information of the system clock, so it is beneficial to ensure the reliability and portability of the circuit.
Second case:
When all clocks in the system do not have a clock rate that is twice the frequency of the other clocks, that is, the situation where multiple clock rates in the system are similar.
At this time, the sampling theorem cannot be satisfied, so in the interface part, it is necessary to isolate other clocks and data through FIFO or DPRAM, and convert other clock information into allowable signals synchronized with the system clock. For example, in a high-speed data acquisition system, the acquisition clock of AD is often relatively high, more than half of the system clock. At this time, the use of synchronization processing cannot meet the timing design.
The third case:
There is mutual sampling of data between multiple clocks in the system.
In this case, two-stage flip-flops can be used to cascade sampling data to avoid metastability.
Fourth case:
Multi-level clock network processing.
The so-called multi-level clock network means that the clock is connected to the clock input of the flip-flop after passing through more than one level of gate circuit.
Due to the limitation of the clock setup-hold time, the use of multiple clock networks should be avoided in FPGA design. The clock network must be simplified in the design, and the enable method or other simplified circuit structure should be used as much as possible.
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Author: Hangzhou Qingcui Technology ALIFPGA
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