ARMv8-A Generic Interrupt Controller(GIC)

This section describes the interrupt controller under the ARM architecture, The Generic Interrupt Controller (GIC)

GIC supports several versions under the ARM architecture, GIC-v1, GIC-v2, GIC-v3, GIC-v4

This series of articles focuses on the GIC-V3 version, and the typical representative of the GIC-V3 version is GIC-500

 

About the characteristics of GIC-500

• GIC-500 can support up to 128Cores
• GIC-500 currently only supports ARMv8 architecture
• GIC supports four types of interrupts
• Support CPU-Interface, Distributor

 

Block diagram between GIC-500 and CPU

• Interrupts are generated through physical interrupt signals (peripheral interrupt signals) or Message-based Interrupts or SGIS. In fact, these are the types of interrupts supported by GIC
• GIC is connected to the CPU through the AXI4-Stream dedicated interface

 

GIC-500's internal layout

You can see that there are two important modules inside the GIC

• Distributor:
• CPU Interface: CPU-Interface is more inclined to the CPU side, each CPU has an Interface.

Look at a more detailed picture

There are several concepts involved in this picture, Distributor, CPU Interface, Redistributor, SGI, PPI, SPI, LPL

You can first look at the following interrupt status and the concept of distributor and CPU-interface

• SPI will be routed from Distributor to Target Redsitributor first, and then to CPU-interface module
• PPI will be routed directly to the local Redsitributor
• SGI interrupt type is triggered by software, it will be routed from core to CPU-interface and Redsitributor module, and then to Dsitributor module, decided to route to one or more CPUs

 

Type of interrupt

Four interrupt types are defined in GIC-v3

• SGI（Software Generated Interrupt）
  1. Interrupt number is between 0-15
  2. Used for communication between cores, interrupts triggered by software, also known as IPI interrupts
• PPI（Private Perpheral Interrupt）
  1. Interrupt number is between 16-31
  2. This type of interrupt is private to each core and is only used when the current core is processing some business. For example, there is a tick interrupt on each core for process scheduling.
• SPI（Shared Perpheral Interrupt）
  1. Interrupt number is between 32-1020
  2. This type of interrupt is an interrupt signal line triggered by peripherals, such as touch screen interrupt of touch, etc.
• LPI（Local-sperical Perpherial Interrupt）
  1. This interrupt not only supports GIC-v1, GIC-v2.
  2. Interrupts based on message type only

 

Distributor

The main function of the arbiter is to prioritize interrupts and distribute SPI and PPI interrupts to the Redistributor and CPU-Interface modules. The register corresponding to the arbiter is GICD_CTLR

• Enable or disable this interrupt ( enabled state )
• Set interrupt priority ( priority )
• Set the trigger mode of this interrupt, whether it is edge trigger or level trigger ( trigger mode )
• Control the state of the interrupt ( interrupt status )
• Enable or disable Securiy ( interrupt safe state )
• Set interrupted Affinity ( interrupted affinity )
• The interrupted routing situation is the CPU that handles the interrupt ( interrupt routing information )

The above is the role of distributor

 

CPU interface

Each CPU corresponds to a CPU Inrerface module. When an interrupt is triggered, the Distributor module will set the interrupt status and route to that CPU

• Control the state of the interruption, whether it has been processed ( state control )
• Identify an interrupt, get the interrupt number of the interrupt ( get the interrupt number )
• Set the priority of the interrupt. If multiple interrupts go to the CPU-interface module at the same time, you need to distinguish the priority ( priority )
• The decision is to mask this interrupt, etc. ( MASK )

 

Interrupted state

• InActive interrupt is not currently triggered
• The Pending interrupt has been triggered and is waiting for the corresponding core to process the interrupt, indicating that this interrupt has been routed to the CPU interface module
• Active means this interrupt is already being processed
• Active and Pending means that the same interrupt is being processed, and the same interrupt is triggered

 

Interrupt state changes

• Inactive -> Pending
  • This interrupt was triggered by the peripheral
• Pending -> Active
  • This interrupt is already handled by the CPU
• Active -> Inactive
  • This interrupt has been processed

 

Interrupt processing flow

• Peripheral or software triggers an interrupt, the status of the interrupt is set to Pending
• This interrupt will go to the Dirtibutor module for priority, status, affinity, and routing to that core
• CPUinterface will route this interrupt to the corresponding core
• At this time, the CPU will access the Interrupt Acknowledge Register (ICC_IAR0) register, obtain the corresponding INTID, and then modify the interrupt status from pending to Active.
• When the CPU has finished processing the interrupt, the software will write this EOI (End of Interrupt) to mark the completion of the interrupt processing
• Change the interrupted state from active to inactive