The main function of AD16 is a circuit schematic drawing and designed according to the principles circuit board PCB. In order to make circuit design, circuit schematics unfinished, there are no mistakes from the principle of the circuit, there is no confusion from the circuit logic, AD16 specially developed schematic circuit simulation program. This allows the existence of design issues, in the first step: drawing circuit schematics stage in time, then the simulation result, improved circuit schematic. This avoids the printed circuit board assembly part until completion of the finished product after the discovery of the problem, a large amount of manpower and resources damages. Also: PCB design, but also on the computer according to the circuit diagram, plotted PCB board in FIG. A PCB then put the computer to get the PCB board PCB plant. AD16 also designed PCB board signal integrity analysis program, the drawing on the PCB board computer simulation signal integrity, so that early detection of A PCB design if a defect exists, in a timely manner to improve over the state. If you draw a good PCB plans, no signal integrity analysis and simulation through PCB board map, to get the factory direct PCB board, PCB board assembly into finished products after completion, it was found defective, it caused great waste.
PCB board signal integrity analysis, refers to a network in PCB, the output waveform of the network, compared with the input waveform to the network, as far as possible similar, less distortion as possible, less delay, less deformable, and less deletions, ringing less and less overshoot. Low frequency digital circuit board PCB, the input signal is processed after the PCB within the network, the network output signal waveform distortion is small, at a high frequency digital circuit board PCB, if the PCB design slightly wrong, the output signal of the network to be tested compared with the input signal of the network, it will have a significant delay, distortion, resulting in the production of non-compliance of the PCB can not be used.
Prerequisites for signal integrity analysis: the need to meet the following conditions in order to perform signal integrity analysis:
- The circuit being tested in the network, must contain IC a signal output pin, this output signal is used as the excitation source of the network. If a network has only R & lt , L , C and other passive components, no transistors, the IC and other active devices, then the passive network, signal integrity analysis can not be performed. In other words: it must be set to test network excitation source.
- In the schematic drawing circuit, the PCB while FIG plate, using the drawing library should use the integrated library, which library integrated circuit part comprises schematic symbols, symbols package, the simulation model, the model signal integrity. If the library does not contain parts of parts integrity model, you must be logged parts manufacturers official website, download the signal integrity model, or find models from other files. And then loaded into the project file to the inside. You can also adjust the model in the schematic.
- Setting the supply network voltage Schematic circuit ( such as 3.3V \ 5V \ 12V , etc. ) , the circuit diagram of the power supply network, is set to 0V .
- Setting PCB board PCB board layer stack: Click Design ------- Layer Stack Manager . The system generally uses the default value.
By analyzing the signal integrity of the PCB, the measurement can be simulated via a network input signal, aliasing distortion and signal crosstalk generated between adjacent network.
Note: When the signal integrity analysis, PCB files being tested must be in the project, can not exist independently of free docment.
Examples of signal integrity analysis:
1, open the project folder: projedts. The project folder comprising: a circuit schematic document file sch PCB board pcb. A PCB open. See below.
2, the PCB provided ply stack management: design ------ layer stack manager ------- pop up the dialog box:
impedance calculation labels, PCB impedance calculation dialog box pops up, as shown below: Click on the map to the right:
On the map, use the default settings.
3, click: design ----- rules ------ Rule dialog box pops up, as shown below:
Found in the lower left portion of the figure above the excitation signal: signal stimulus, the signal stimulus top right click, select new rule, as shown below:
In the right column of the figure, the parameters of the excitation signal is provided, the system uses the default value.
- And the set voltage network: the lower left corner in the figure below, click: Supply NET , select the new rule.
In the following figure, the best way to the right emerging power network, the network voltage is set to GND is 0V, the voltage VCC set is 5V. Then click OK.
- Select tools ----- signal integrity ------ pop up a dialog box in:
Click on the map model assignnent configuration integrity analysis model, the following dialog box will pop up:
On the table name explanation:
Not match: represents AD16 program integrity analysis model of the device not found. People need to be specified.
Low confidence: program automatically assigns a model for the device, but the confidence level is low.
Medium confidence: Intermediate confidence.
High confidence: confidence is very high.
Model found: model of the device has been found.
User modifined: the user to modify the model.
Model added：用户创建了模型。
修改期间完整性分析模型的步骤：双击上图中要修改模型器件的status部分-------弹出下图：完整性分析模型修改对话框------在TAPE选项中选择器件的类型-------在technology选项中选择驱动类型-------也可以从外部文件导入与该器件相关联的IBIS模型-------大家IMPORT IBIS-------选择从器件厂商哪里得到的IBIS模型即可-----单击OK。单击上图左下角：update model schematic,将修改后的模型更新到原理图中。单击上图中右下角的analyze design标签------程序进入信号完整性分析------弹出：signal integrity分析网络状态表格：见下面第二图：
上面的网络完整性分析表格：status，最左的net：代表网络名称，作数第二：status，标明这个网络是否通过了完整性分析（failed：没有通过）、没有分析（not analyze）、分析通过（passed）。上表中的falling edge overshoot:代表脉冲下降沿过冲，falling edge undershoot:代表脉冲下降沿衰减。Rising edge overshoot:代表上升沿过冲。Rising edge undershoot：代表上升沿衰减。
- 怎样查看上面网络表中某一个网络的完整性分析结果：右键单击上表中第三个网络：TXB-------在下拉菜单中选择details细节--------弹出下图：full result（该网络分析的详细结果）。
- 查看网络输出端的反射波形：
双击上图中网络名称：TXB-------就可把网络TXB运动到上图中的右侧：net（网络框中）-----此时上图右下角灰色（无效）的reflections变成黑色（有效）-------见下图：
单击上图右下角的reflections-------显示输入波形和输出带有反射的波形：见下图。
右键单击上图中右上角红色的TXB-U2 13-NOterm-------在弹出的下拉菜单中选择光标A和光标B，见下图：
利用上图中的光标A和光标B，精确测量，测量结果显示在sin data（在显示信号完整性分析的AD16窗口前提下，AD16屏幕的右下角，显示有：sin data标签）中。
9：网络输出端式接不同的匹配电阻，以消除输出端的反射波形。见下图的右下角：给出了网络输出端试结串联电阻、并联电阻、串联电容、并联电容、并联D时的不同情况下，分别查看哪种情况下网络输出端的反射波形最小。试现在在网络输出端串联电阻的方法：serial res。如下面的第二图所示：
（上图右下角no termination:表示输出端没有接任何匹配电阻）
上图serial res：表示网络输出端串联了匹配电阻。上图中:min：代表匹配电阻取值的最小值：25欧，max:代表匹配电阻取值的最大值是150欧，这两个数值可以有用户任意修改。设定完最大值和最小值后，选中进行扫描：perform sweep，单击上图右下角的reflection------匹配电阻取值在25欧--------150欧之间联系均匀改变时，网络输出端反射波形，在哪个欧姆时最小。以此找到匹配电阻的最佳电阻值。
10、PCB板相邻网络的串扰分析：双击上图中左上角的TXB，使之选中进入上图右上角的NET内，再双击相邻的网络RTSB，也选中到右上角的NET内，右键单击右上角NET内的TXB,在下拉菜单中选择：set aggressor，把TXB设定为入侵者（干扰源），RTSB网络就是受干扰网络了。单击上图右下角的cross talk标签，分析串扰，过一会就显示串扰的波形。