1. chip initialization
Many people can not imagine, inside the SDRAM chips and a logic control unit, and has a mode register to provide the control parameters. Therefore, each time you turn on the SDRAM must first initialize the control logic core. For refresh precharge and hereinafter have the meanings about, critical stage in that a mode register (MR, ModeRegister) is provided, referred to MRS (MR Set), this work carried out by the north bridge chip under control of the BIOS, the information register provided by the address lines.
SDRAM mode register is controlled operating parameters: 0/1 address lines provide different signals to obtain different parameters. After setting to MR, we began to enter the normal working condition;
2. The line is valid
After initialization, in order for a L-Bank in addressing the array, we must first determine the row (Row), so that in the active state (the Active), and then determine the column. Although be addressed prior to chip select and L-Bank, but they may be performed simultaneously with the active line.
As can be seen from the figure, the CS #, L-Bank addressed simultaneously, RAS (Row Address Strobe, row address strobe) is also active. An address lines at this time send a specific row address. FIG A0-A11 is, a total of 12 address lines, as is the binary representation, so a total of 4096 lines (212 = 4096), different values A0-A11 determines the specific row address. Since the effective line corresponding L-Bank is also active, so the lines may also be referred to as L -Bank effective effective.
3. In the column to read and write
After the row address is determined, it is necessary for addressing the column address. However, the address lines A0-A11 are still used by the row address (in this example) . Yes, in the SDRAM, a row address and column address lines are shared . However, the read / write command is issued how it? In fact, not a signal is sent to read or write an explicit order, but to achieve the purpose of the read / write control chip can be written by the state . Obviously WE # signal is a key . When WE # is not valid, of course, it is a read command.
FIG basic operation is the SDRAM command, through various combinations of the control / address signals to complete (H denote high-level, L denote low-level, X represents an average power level has no effect). In this table, in addition to the self-refresh command, all commands are valid CKE default. For the self-refresh command, the following Detailed there. Column address signal and read and write commands are issued simultaneously. Although the address line and a common row address, but the CAS (Column Address Strobe, Column Address Strobe) signal may be distinguished from a different row and column addressing, with A0-A9, A11 (in this example) of the column address to determine the specific .
However, when the column write and read commands must be sent with a valid command line interval, this interval is defined as the tRCD, i.e. RAS to CAS Delay (RAS to CAS delay), we can also be understood as a row strobe period, which should the response time is the memory array chip electronic component (from one state to another state change process) developed by the delay. T the RCD is an important timing parameters of the SDRAM can be adjusted through the BIOS through the motherboard Northbridge chip, but can not exceed a predetermined range of manufacturers. Generalized tRCD clock cycles (tCK, Clock Time) is the number of units, such as tRCD = 2, represents a delay period of two clock cycles, specific to an exact time, it will have to set the clock frequency for PC100 SDRAM, tRCD = 2, representative of 20ns delay for PC133 was 15ns.
4. Data readout
After the column address is selected, it has been determined that a specific memory cell, all that remains is the data output to the memory data bus through the I / O channel (DQ). But after issuing CAS, still after a certain time to output data, and a read command sent from the CAS to the period of the first data output, is defined as CL (CAS Latency, CAS latency) . Since only appear when reading the CL, it is also known as read latency of CL (RL, the Read Latency) . CL units to tRCD same number of clock cycles, the clock frequency is determined by the specific time-consuming. However, CAS is not only served in the storage unit after CL cycles. CAS and RAS are in fact the same as the moment arrived, but the response time is faster CAS number. why? Suppose 'bit of n bit width of the chip, the number of columns is c, then a row address strobe n × c to memory banks, and a column address strobe only n memory banks. But the response time is stored in the body of the transistor will cause data can not be in the same edge trigger with CAS, will certainly be delayed at least one clock cycle. Due to the volume of the chip, the memory cell capacitance is small, the signal to be amplified to ensure its effective visibility, this amplification / driver responsible for the S-AMP, a bank corresponding to a channel S- AMP . But it must be a lead time in order to ensure the strength of the transmission signal (voltage comparison also prior to determination logic level), therefore the data from the I / O bus clock before a rising edge of the data output start, i.e., the data It has been transmitted to the S-AMP, say at this time the data has been triggered, after a certain driving time of the final output to the transmission of data I / O bus, which we call tAC (Access time from CLK, the clock trigger access time). tAC unit is ns, for different frequencies have different clearly defined, but must be less than one clock cycle, otherwise they will be too long to access the lower efficiency. For example, the clock cycle PC133 7.5ns, tAC is 5.4ns. It is emphasized that, while each data reading has tAC, comprising a continuous reading, only during the first data transmission begins tAC while the second data.
CL value can not exceed the design specifications of the chip, otherwise it will lead to memory instability, or even can not be switched (overclocking players should have experience) , but it can not be changed in the interim before data read. CL cycle is provided during initialization boot MRS stage, the BIOS thereof typically allow the user to adjust and control the Northbridge chip BIOS information CL in register MR change by address lines A4-A6 boot. However, it can be seen from the structure of FIG bank, original logic state of a capacitor after the read operation, due to the discharge becomes a logic 0. Therefore, before closing the current row in the DRAM to ensure reliability of data, the bank to be rewritten any original information, the task passes the data to complete the refresh amplifiers, which according to logic level state, the data rewrite (overwrite the logic 0 is not), since the output of this operation is synchronized with the data and do not conflict, so no new delay overwritten. Later, through improved technology, refresh amplifier is canceled, its function replaced by S-AMP, because it remains in reading the logic state of the data, played a role of a Cache, sent to it by a direct read again, do not have a new address output, and the data rewriting operation can be completed during the precharge phase.
Question: Why after reading the high level will not go away? The answer to the above paragraph;
The data write
Data write operation is also carried out after tRCD, but this time without the CL (remember, CL appears only in a read operation), and a timing diagram for row addressing and column addressing as described above, except column hunt when the address, WE # is active.
It is seen from the figure, since the data signal emitted by a control terminal, an input chip without making any adjustment, simply transmitted directly to the data input register, and then the charging operation of the storage capacitor by the write drivers, so the data can be CAS sent simultaneously, which means that the write latency is 0. However, real time data is not written to the storage capacitor, because the transistor gate (as it is the same as when reading) and the capacitor must be charged for some time, so the real writing data requires a certain period. To ensure reliable data written will allow sufficient write / correction time (tWR, Write Recovery Time), this operation is also referred to as write-back (Write Back). tWR occupy at least one clock cycle or more point (the higher the clock frequency, the more tWR occupancy period), the influence will be further talk about it later.
6. Burst Mode
Burst (Burst) refers to the way in the same row of adjacent memory cells continuously for data transmission, the number of consecutive transmissions involved in the storage unit (column) is the burst length (Burst Lengths, abbreviated BL). At the moment, because the memory controller is a read / write data bits wide P-Bank, which is 8 bytes, but the data is less than 8 bytes are rare in reality, it is generally to go through multiple cycles transmission of data. The above-mentioned read / write operation, a memory cell is one of addressed, if to be continuously read / written but also for the next cell of the current memory cell is addressed, is to keep the column address is transmitted and read / write command (row address change, so no longer on the line addressing). Although the read / write latency can make the same transfer data in I / O terminal is continuous, but it takes up a lot of memory control resources to enter new command for continuous transmission of data, efficiency is very low (early FPE / EDO memory data transfer is continuous in this manner). For this purpose, the burst transmission techniques have been developed, as long as the specified starting column address and the burst length, the memory will automatically turn back a corresponding number of memory cell read / write operation without the need for the controller to continuously provide column address. Thus, a first pen in addition to data transmission requires a number of cycles (before the main delay is generally tRCD + CL), the data for each subsequent cycle only one can be obtained. Introducing many northbridge words similar in both X-1-1-1, refers to mean, it represents wherein X represents a first number of cycles used by the pen.
Continuous non-burst read mode: transmitting a burst but not individually addressable successively, at this time may be equivalent to BL = 1. Although it can make a continuous transmission of data, but each time sending a column address and command information, control resource consumption significantly.
Burst continuous reading mode: If the specified starting column address and the burst length, addressing and reading of data performed automatically, as long as control and two burst read command interval period (the same as the BL) can be done continuous burst transmission. As the value of BL, is provided not just the front or the provisional decision data transmission. MRS stage initialization process mentioned above is necessary to set the BL . Currently available options are 1,2,4,8, full-page (Full Page), a common set of 4 and 8 . By the way, BL can change the Northbridge chip design has a great relationship, not everyone can be like Northbridge adjustment to adjust the CL as BL. Some chipsets BL is set death is not changed, such as the Intel chipset BL are substantially 4, so there would be no option BL is disposed corresponding motherboard BIOS. And because the data transmission system is based on the current SDRAM 64bit / cycle, so in some BL with the BIOS also QWord (4 words, i.e. 64bit) expressed. The 4QWord that BL = 4. Further, except for a phase in MRS BL set value, but also to determine the specific read / write operation mode and a burst mode of transmission. Burst read / burst write, read and write operations are represented by a burst transfer, each read / write operation is continued for the length BL set, which is the conventional setting. Burst read / single write, a read operation is represented by a burst transfer, only one write operation is performed individually. A burst transfer mode represents transmission order of the memory cell involved in a burst period. Refers to sequential transmission is sequentially read from the starting cell. If BL = 4, the starting cell number is n, the order is n, n + 1, n + 2, n + 3. Disrupt the normal transmission is interleaved order of data transmission (such as the first cell transmission is performed is n, and the second transmission unit is not the n + 2 n + 1), as for interleaving rules in the SDRAM specification a detailed definition of the table, but in this space and the need for this consideration is not listed.
7. precharging
Since the exclusive addressing specific SDRAM, it is finished after performing read and write operations, if addressed to another row of the same L-Bank, should the original active (working) row is closed, re-transmitting the row / column address . L-Bank prior work off-line, ready to open a new row operation is a precharge (Precharge). Controlled by a precharge command, setting may be assisted by allowing the chip to automatically precharging after each read or write operation. In fact, the working is a pre-charge line data rewriting all memory bank, the row address and reset, while the release of S-AMP (rejoining the comparison voltage, the capacitor voltage is generally 1/2 to help determine read logic level of the data, because the S-AMP logic value is judged by comparing a reference voltage with the line voltage of the storage position), to the preparation of the new row. Specifically, the data is written back to the SAMP, even if there is no bank will be worked by the works of the strobe storage capacitor is disturbed, so it needs to be SAMP reading rewritten. At this time, the capacitor charge (or voltage it produces) will be determined according to the logic state (also required when reading), this should set a threshold value, typically the capacitance of a half, than it logic 1, overwriting, otherwise a logical 0 is not rewritten (equal to the discharge). For this reason, now basically the other terminal of the capacitor to access a specified voltage (i.e., 1/2 capacitor voltage), instead grounded to help compare the determined time of overwriting. Now we go back and look at the command of a timing chart when read and write operations, address line A10 can be found that the control whether automatically read after precharge current L-Bank, which is the above-mentioned "auxiliary setting . " In a separate precharge command, A10 then control is designated L-Bank or all L-Bank (when there are a plurality of L-Bank is active / active state) is precharged, the former need to provide L- Bank address, which is simply placed in the high level signal A10. After issuing the precharge command, some time to be allowed to send a new command to open a row active RAS work line, the interval is referred to as tRP (Precharge command Period, active precharge cycle). And tRCD, CL as, tRP units are number of clock cycles, depending on the value of the specific clock frequency dependent.
Auto precharge start time as this FIG., But no separate precharge command and a read command is issued, A10 address line is set to be high (to allow auto-precharge). Visible control the precharge start time is important, it can be addressed immediately enter a new line at the end of the read operation, ensure operational efficiency. Myth: In case the reader must take into account the write-back delay some articles stressed after the operation due to the write-back read / write operations have some delay, but the introduction of this article writing can be seen even reading immediately rewrite design, because it is synchronized with the output data, there is no delay. Only perform other operations after a write operation, will have influence in this regard. Although the write operation is zero delay, but the real data is written to every need a sufficient period to ensure that, this time to write back cycle (tWR). So precharge and write operations can not be performed at the same time, it must in order to issue a precharge command after tWR, to ensure reliable data written, rewritten or data may be wrong, which resulted in a write-back delay.
The picture shows the precharge timing chart of a data write operation: Note tWR parameters which, due to its presence, the precharge operation delayed, resulting in write-back delay.
8. Refresh
It is called DRAM, because it must constantly refresh (Refresh) to retain data, so it is most important DRAM operation. Refresh operation and precharge operation of overwriting, are read by the first S-AMP write. But why have the precharge operation but also to refresh it? Because pre-charging is a L-Bank or all the working line operation, and is irregular, while the refresh cycle is fixed, all rows are sequentially operated in order to keep those banks not experienced for a long time rewritable the data. However, all precharge except that L-Bank, Row herein all refer to the same L-Bank address line, and the row address precharge working in the respective L-Bank is not necessarily the same. So to repeat more than once every refresh long? Currently accepted standard, the data bank storage capacitance limit the effective period is 64ms (milliseconds, 1/1000 seconds), that is to say each line of the refresh cycle period is 64ms. Such is the refresh rate: the number of lines / 64ms. When we look at memory specifications, often you see the logo 4096 Refresh Cycles / 64ms or 8192 RefreshCycles / 64ms, where the 4096 and 8192 represents the number of rows in the chip of each L-Bank. Refresh command once valid line, the transmission interval is changed with the number of rows, row 4096 is 15.625μs (microseconds, 1/1000 ms), 8192 to row 7. 8125μs. Refresh operations are divided into two types: auto-refresh (Auto Refresh, referred to as AR) and self refresh (Self Refresh, referred to as SR). Whatever the refresh mode, you do not need to provide external row address information, because this is an internal automatic operation. For AR, a SDRAM internal row address generator (also called refresh counter) is used to automatically generate row addresses sequentially. Since refresh is performed for all banks in a row, so no column addressing, or CAS valid before RAS. So, AR, also known as CBR (CAS Before RAS, a column in the row ahead of positioning) refresh. Since the refresh involves all L-Bank, so refresh process, all L-Bank are stopped, and the time occupied by each refresh is 9 clock cycles (PC133 standard), can then enter the normal operating state, this means that over a period of nine clock, can only wait for all the work orders can not be executed. Then again to refresh the same row after 64ms, again and again circulated refresh. Clearly, the performance of the refresh operation of the SDRAM will certainly be affected, but this is no way of things, but also with respect to DRAM SRAM (static RAM, can still retain data without refreshing) costs while achieving cost advantages of pay. SR is mainly used for data storage in the low-power sleep mode state, the application of this aspect is the best known STR (Suspend to RAM, Hibernate suspend in memory). AR command when issuing the CKE inactive state, the SR mode is entered, then the system clock will not work, but the refresh operation according to the internal clock. During SR all external signals except CKE are valid (no external refresh instruction provided), only to re-enable CKE effective to exit self-refresh mode and enter the normal operating state. Is mainly used for data storage in the low-power hibernation state, the application of this aspect is the best known STR (Suspend to RAM, Hibernate suspend in memory). AR command when issuing the CKE inactive state, the SR mode is entered, then the system clock will not work, but the refresh operation according to the internal clock. During SR all external signals except CKE are valid (no external refresh instruction provided), only to re-enable CKE effective to exit self-refresh mode and enter the normal operating state. Is mainly used for data storage in the low-power hibernation state, the application of this aspect is the best known STR (Suspend to RAM, Hibernate suspend in memory). AR command when issuing the CKE inactive state, the SR mode is entered, then the system clock will not work, but the refresh operation according to the internal clock. During SR all external signals except CKE are valid (no external refresh instruction provided), only to re-enable CKE effective to exit self-refresh mode and enter the normal operating state.
9. The data mask
When telling a read / write operations, we talked about the burst length. If BL = 4, then that once the 4 × 64bit data transfer. However, if one of the second tranche of data is not needed, how to do? They are also transmitted it? To shield unnecessary data, it uses the mask data (Data I / O Mask, referred to as the DQM) technology. By DQM, you can control the memory I / O data which is input or output port canceled.
It should be emphasized that, at the time of reading, the data will still be masked outgoing from the bank, but at a masked "mask logic unit." DQM controlled by the North Bridge, in order to accurately screen a P-Bank bit width in each byte, each with eight DIMM DQM signal lines, each signal for a byte. Thus, chip for 4bit bit width, two devices share a DQM signal line for 8bit bit width, one chip occupies a DQM signal, and for 16bit bit width, then two DQM pins. SDRAM official regulations take effect after issuing two clock cycles when reading DQM, in writing, DQM and write commands as immediate results.
