DRAM (Dynamic Random Access Memory), namely dynamic random access memory, the most common scenario is the computer and the phone's memory, it is indispensable part of the current circuit system, and a more detailed article will explain the image data stored in DRAM and the whole process of reading data.
1. DRAM minimum unit composed of a single tube
a single tube mass memory DRAM is the only option. The read-write circuit comprises a switching transistor and a storage capacitor, as shown below. Use of a storage capacitor for storing data, if there on the charge storage capacitor, said storage unit stores a 1 if the storage O.
First, know two premises: First, the voltage applied to the power supply voltage of the storage capacitor 1/2 (Vcc / 2); secondly, because electrons are negatively charged, and therefore, the multiple electron potential more low. To facilitate clarify the concept, we set the top of the reservoir potential of 0V, the potential of the bottom of the reservoir as Vcc.
Three basic operations of the memory cell
three basic operations are stored data, write data and read data three. Similarly, easy to understand, these three processes with the storage reservoir analogy to let go of water, some of the image slightly.
Information storage
schematic data stored as shown below, the shutter is closed when the reservoir (row address lines Vth = 0V), the water can not flow out of the reservoir, the water can not flow upstream, water stored in the reservoir remains unchanged, it is possible to achieve the purpose of storing data. The water level on the use of high and low to represent.
Write data
written information can be divided into write "0" in the case and write "1" in the case of two kinds. Write 0 to the case to illustrate.
Specific order: First, because before there may be information on the state of the reservoir may be filled with water or water of empty water. Then, the upstream waterway (column address strobe path) is full of water to the water level rises, corresponds to a low state (column address lines Vcc = 0V). Finally, the row address control circuit (Vth = high) of the upstream water gate is opened, because the upstream waterway (column address line Vcc = 0V) to high water level are full state, in accordance with the state of the reservoir water level, will fill the pool full, so that the reservoir becomes a high level (low state 0).
Analogy, in the case of goods through the canal locks are also very easy to understand, all of you to make up the brain.
Read the data
while reading DRAM memory cells, the column address routing is generally used 1 / 2VCC precharge techniques. To read 0 as an example.
First, all full reservoir level (0V voltage), the first predetermined water level in the watercourse 2.5V; then open the sluice, that is, the row address lines at a high level, so that the water reservoir is returned to waterways (column address lines) , since a very small amount of water in the reservoir, so that it can only slightly increase the water level in the watercourse. When the sense amplifier detects the water level of the watercourse a difference delta, you can identify the reservoir (capacitance) of the data 0.
Wherein, as the water level changes: delta = 5/2 (1 + Cb / Cs), waterway (column address line) is greater than the capacitance reservoir (row address line) capacity. The specific process complicated than this, but this analogy can understand the working principle, enough.
Oh, yes, worse forget, if there is no water in the waterway outside to supplement the reservoir, the water level in the reservoir due to evaporation, infiltration, water will gradually reduce and finally dried up. Therefore, the schematic is the same capacitance, a slight delay in the detection refresh charge, which is the dynamic of the root cause.