SystemVerilog范围解析运算符

范围解析运算符::用于引用类范围内的标识符。范围解析运算符::的左侧应该是类类型名称，package包名称，covergroup类型名称，coverpoint或cross名称，typedef名称。 运算符的右侧应为标识符，如变量或方法名称。

为什么需要范围解析运算符？

类和其他作用域可以具有相同的标识符名称，如果在未指定作用域的情况下进行引用，则可能会导致名称空间冲突。 范围解析运算符::唯一地标识给定类的成员或参数。

它们还用于从类外部访问类的静态变量和方法，参数以及局部参数。 它还允许从子类中访问基类的公共成员和受保护成员。

例子 1.定义外部函数

class ABC;
  int   data;
 
  extern virtual function void display();
endclass
 
// Definition of an external function using scope
// resolution operator
function void ABC::display();
  $display("data = 0x%0h", data);
endfunction
 
module tb;
  initial begin  
    ABC abc = new();
    abc.data = 32'hface_cafe;
    abc.display();
  end
endmodule
 
Simulation Log
ncsim> run
data = 0xfacecafe
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

2.访问静态方法和函数

class ABC;
  static int   data;
 
  static function void display();
    $display("data = 0x%0h", data);
  endfunction
endclass
 
module tb;
  initial begin
        ABC a1, a2;
 
        // Assign to static variable before creating 
        // class objects, and display using class_type and
        // scope resolution operator
    ABC::data = 32'hface_cafe;
    ABC::display();
 
        a1 = new();
        a2 = new();
        $display ("a1.data=0x%0h a2.data=0x%0h", a1.data, a2.data);
  end
endmodule
 
Simulation Log
ncsim> run
data = 0xfacecafe
a1.data=0xfacecafe a2.data=0xfacecafe
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

3. Using package

package my_pkg;
  typedef enum bit {FALSE, TRUE} e_bool;
endpackage
 
module tb;
  bit val;
 
  initial begin
    // Refer to types that have been declared
    // in a package. Note that package has to 
    // be included in compilation but not 
    // necessarily "imported"
    val = my_pkg::TRUE;
    $display("val = 0x%0h", val);
  end
endmodule
 
Simulation Log
ncsim> run
val = 0x1
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

4. Avoid namespace collision

package my_pkg;
  typedef enum bit {FALSE, TRUE} e_bool;
endpackage
 
import my_pkg::*;
 
module tb;
  typedef enum bit {TRUE, FALSE} e_bool;
 
  initial begin
    e_bool val;
 
    // Be explicit and say that TRUE from my_pkg
    // should be assigned to val
    val = my_pkg::TRUE;
    $display("val = 0x%0h", val);
 
    // TRUE from current scope will be assigned to
    // val
    val = TRUE;
    $display("val = 0x%0h", val);
  end
endmodule
 
Simulation Log
ncsim> run
val = 0x1
val = 0x0
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit

参考文献：
【1】https://www.chipverify.com/systemverilog/systemverilog-scope-resolution-operator