本实例特点：
- 波特率可调；
- 发送位宽可调（8位以内）；
- 校验值可选择；
- 接收/发送 值可校验；
- 停止位可选择；（1位、1.5位、2位）。
- 本实例已自行仿真并UART传输验证，如有错误，欢迎指正，不胜感激。
1、波特率时钟模块
1 /*************************************************** 2 * Module Name :UART_Baud_CLK 3 * Engineer : 王小虎 4 * Target Device : EP4CE10F17C8 5 * Tool versions : Quartus II 13.0 6 * Create Date : 2019 7 * Revision : v1.0 8 * Description :UART 波特率时钟输出 9 **************************************************/ 10 module UART_Baud_CLK( 11 clk, 12 rst_n, 13 UART_En, 14 UART_Done, 15 Baud_Set, 16 Baud_CLk, 17 Baud_CLk_half 18 ); 19 //=================================<端口>=========================== 20 //-- 物理端口 21 input clk; //时钟信号 22 input rst_n; //复位信号 23 //-- 上级系统通信 24 input UART_En; //UART使能 25 input UART_Done; //UART失能 26 input [3:0]Baud_Set; //波特率选择 27 output reg Baud_CLk; //输出波特率时钟 28 output reg Baud_CLk_half; //输出加倍波特率时钟 29 //-- 内部信号 30 reg UART_state; //传输状态 31 reg [19:0]Baud_cnt; //波特率计数值 32 reg [19:0]cnt; //波特率计数器 33 //------------------------------------------------------------------- 34 //--序号01 功能描述：波特率时钟输出 35 //------------------------------------------------------------------- 36 //--UART_state 37 always@(posedge clk or negedge rst_n) 38 if(!rst_n) 39 UART_state <= 1'b0; 40 else if(UART_En) 41 UART_state <= 1'b1; 42 else if(UART_Done) 43 UART_state <= 1'b0; 44 else 45 UART_state <= UART_state; 46 47 //--波特率计数器 48 always@(posedge clk or negedge rst_n) 49 if(!rst_n) 50 cnt <= 20'd0; 51 else if(UART_state)begin 52 if(cnt == Baud_cnt) 53 cnt <= 20'd0; 54 else 55 cnt <= cnt + 1'b1; 56 end 57 else 58 cnt <= 20'd0; 59 //--波特率时钟 60 always@(posedge clk or negedge rst_n) 61 if(!rst_n) 62 Baud_CLk <= 1'b0; 63 else if(cnt == Baud_cnt) 64 Baud_CLk <= 1'b1; 65 else 66 Baud_CLk <= 1'b0; 67 //--波特率时钟 half 68 always@(posedge clk or negedge rst_n) 69 if(!rst_n) 70 Baud_CLk_half <= 1'b0; 71 else if( cnt == (Baud_cnt >> 1'b1) ) 72 Baud_CLk_half <= 1'b1; 73 else 74 Baud_CLk_half <= 1'b0; 75 //------------------------------------------------------------------- 76 //--序号02 功能描述：波特率计数查找表 77 //------------------------------------------------------------------- 78 always@(*) 79 begin 80 case(Baud_Set) 81 4'd0 : Baud_cnt = 20'd454544; //110 82 4'd1 : Baud_cnt = 20'd166666; //300 83 4'd2 : Baud_cnt = 20'd83332 ; //600 84 4'd3 : Baud_cnt = 20'd41666 ; //1200 85 4'd4 : Baud_cnt = 20'd20832 ; //2400 86 4'd5 : Baud_cnt = 20'd10416 ; //4800 87 4'd6 : Baud_cnt = 20'd5207 ; //9600 88 4'd7 : Baud_cnt = 20'd3471 ; //14400 89 4'd8 : Baud_cnt = 20'd2603 ; //19200 90 4'd9 : Baud_cnt = 20'd1735 ; //28800 91 4'd10 : Baud_cnt = 20'd1301 ; //38400 92 4'd11 : Baud_cnt = 20'd892 ; //56000 93 4'd12 : Baud_cnt = 20'd867 ; //57600 94 4'd13 : Baud_cnt = 20'd433 ; //115200 95 4'd14 : Baud_cnt = 20'd390 ; //128000 96 4'd15 : Baud_cnt = 20'd194 ; //256000 97 default:Baud_cnt = 20'd5207 ; //9600 98 endcase 99 end 100 101 endmodule
2、发送模块
1 /*************************************************** 2 * Module Name : UART_Tx_module 3 * Engineer : 王小虎 4 * Target Device : EP4CE10F17C8 5 * Tool versions : Quartus II 13.0 6 * Create Date : 2019 7 * Revision : v1.0 8 * Description : UART发送模块 9 **************************************************/ 10 module UART_Tx_module( 11 clk, 12 rst_n, 13 UART_Tx_En, 14 UART_Tx_Data, 15 UART_Tx_Width, 16 STOP_Bit, 17 Parity_Set, 18 Baud_CLk, 19 Baud_CLk_half, 20 UART_Tx_Done, 21 UART_Tx 22 ); 23 //=================================<端口>=========================== 24 //-- 物理端口 25 input clk; //时钟信号 26 input rst_n; //复位信号 27 output reg UART_Tx; //UART输出信号 28 //-- 上级系统通信 29 input UART_Tx_En; //UART_Tx发送使能 30 input [7:0]UART_Tx_Data; //待发送数据 31 input [3:0]UART_Tx_Width; //待发送数据位宽 32 input [1:0]STOP_Bit; //停止位位宽设置 00:1 01:1.5 10:2 33 input [2:0]Parity_Set; //校验位设置 0:无校验 1:奇校验 34 // 2:偶校验 3:置1 4:置0 35 input Baud_CLk; //波特率时钟 36 input Baud_CLk_half; //波特率半时钟 当1.5停止位时使用 37 output reg UART_Tx_Done; //单次发送结束 38 //-- 内部信号 39 reg [7:0]data; //待发送数据寄存器 40 reg [3:0]data_width; //待发送数据位宽寄存器 41 reg [1:0]StopBit; //停止位位宽寄存器 42 reg [2:0]Parity; //校验方式寄存器 43 reg Parity_Bit; //校验位数值 44 reg [3:0]cnt; //序列机计数 45 reg Tx_State; //发送状态 46 reg [7:0]add_data; //自加数 47 reg add_s; //累加器 48 //------------------------------------------------------------------- 49 //--序号01 功能描述：寄存上级数据或指令 50 //------------------------------------------------------------------- 51 //--data 52 always@(posedge clk or negedge rst_n) 53 if(!rst_n) 54 data <= 8'd0; 55 else if(UART_Tx_En) 56 data <= UART_Tx_Data; 57 else 58 data <= data; 59 //--data_width 60 always@(posedge clk or negedge rst_n) 61 if(!rst_n) 62 data_width <= 4'd0; 63 else if(UART_Tx_En) 64 data_width <= UART_Tx_Width; 65 else 66 data_width <= data_width; 67 //--StopBit 68 always@(posedge clk or negedge rst_n) 69 if(!rst_n) 70 StopBit <= 2'd0; 71 else if(UART_Tx_En) 72 StopBit <= STOP_Bit; 73 else 74 StopBit <= StopBit; 75 //--Parity 76 always@(posedge clk or negedge rst_n) 77 if(!rst_n) 78 Parity <= 3'd0; 79 else if(UART_Tx_En) 80 Parity <= Parity_Set; 81 else 82 Parity <= Parity; 83 //------------------------------------------------------------------- 84 //--序号02 功能描述：发送数值功能 85 //------------------------------------------------------------------- 86 //-- 校验值计算 87 always@(posedge clk or negedge rst_n) 88 if(!rst_n) 89 Parity_Bit <= 1'b0; 90 else if(Tx_State)begin 91 case(Parity) 92 3'd0:Parity_Bit <= 1'b0; 93 3'd1:Parity_Bit <= ~add_s; 94 3'd2:Parity_Bit <= add_s; 95 3'd3:Parity_Bit <= 1'b1; 96 3'd4:Parity_Bit <= 1'b0; 97 default:Parity_Bit <= 1'b0; 98 endcase 99 end 100 else 101 Parity_Bit <= 1'b0; 102 103 //-- 发送计数器 104 always@(posedge clk or negedge rst_n) 105 if(!rst_n) 106 cnt <= 4'd0; 107 else if(Tx_State)begin 108 if(Baud_CLk)begin 109 if(cnt == data_width && Parity) 110 cnt <= 4'd9; 111 else if(cnt == data_width && !Parity) 112 cnt <= 4'd10; 113 else if(cnt == 4'd10 && !STOP_Bit) 114 cnt <= 4'd12; 115 else 116 cnt <= cnt + 1'b1; 117 end 118 else if(Baud_CLk_half && (cnt >= 4'd11) &&(StopBit == 2'b01)) 119 cnt <= cnt + 1'b1; 120 else 121 cnt <= cnt; 122 end 123 else 124 cnt <= 4'd0; 125 //-- 发送结束标志 126 always@(posedge clk or negedge rst_n) 127 if(!rst_n) 128 UART_Tx_Done <= 1'b0; 129 else if((StopBit == 2'd0) && Baud_CLk && (cnt == 4'd10)) 130 UART_Tx_Done <= 1'b1; 131 else if((StopBit == 2'd1) && Baud_CLk_half && (cnt == 4'd11)) 132 UART_Tx_Done <= 1'b1; 133 else if((StopBit == 2'd2) && Baud_CLk && (cnt == 4'd11)) 134 UART_Tx_Done <= 1'b1; 135 else 136 UART_Tx_Done <= 1'b0; 137 //-- 发送状态 138 always@(posedge clk or negedge rst_n) 139 if(!rst_n) 140 Tx_State <= 1'b0; 141 else if(UART_Tx_En) 142 Tx_State <= 1'b1; 143 else if(UART_Tx_Done) 144 Tx_State <= 1'b0; 145 else 146 Tx_State <= Tx_State; 147 //-- 发送序列机 148 always@(posedge clk or negedge rst_n) 149 if(!rst_n) 150 UART_Tx <= 1'b0; 151 else if(Tx_State)begin 152 case(cnt) 153 4'd0 : UART_Tx <= 1'b0; 154 4'd1 : UART_Tx <= data[0]; 155 4'd2 : UART_Tx <= data[1]; 156 4'd3 : UART_Tx <= data[2]; 157 4'd4 : UART_Tx <= data[3]; 158 4'd5 : UART_Tx <= data[4]; 159 4'd6 : UART_Tx <= data[5]; 160 4'd7 : UART_Tx <= data[6]; 161 4'd8 : UART_Tx <= data[7]; 162 4'd9 : UART_Tx <= Parity_Bit; 163 4'd10: UART_Tx <= 1'b1; 164 4'd11: UART_Tx <= 1'b1; 165 default:UART_Tx <= 1'b1; 166 endcase 167 end 168 else 169 UART_Tx <= 1'b1; 170 //------------------------------------------------------------------- 171 //--序号03 功能描述：累加器 172 //------------------------------------------------------------------- 173 //--add_data 赋值及循环右移 174 always@(posedge clk or negedge rst_n) 175 if(!rst_n) 176 add_data <= 8'd0; 177 else if(UART_Tx_En) 178 add_data <= UART_Tx_Data; 179 else if(Tx_State)begin 180 if(Baud_CLk) 181 add_data <= {add_data[0],add_data[7:1]}; 182 else 183 add_data <= add_data; 184 end 185 else 186 add_data <= 8'd0; 187 188 //--累加器 189 always@(posedge clk or negedge rst_n) 190 if(!rst_n) 191 add_s <= 1'b0; 192 else if(Tx_State)begin 193 if( cnt < data_width && Baud_CLk ) 194 add_s <= add_s + add_data[0]; 195 else 196 add_s <= add_s; 197 end 198 else 199 add_s <= 1'b0; 200 201 endmodule
3、接收模块
1 /*************************************************** 2 * Module Name : 3 * Engineer : 王小虎 4 * Target Device : EP4CE10F17C8 5 * Tool versions : Quartus II 13.0 6 * Create Date : 2019 7 * Revision : v1.0 8 * Description : 9 **************************************************/ 10 module UART_Rx_module( 11 clk, 12 rst_n, 13 UART_Rx_En, 14 UART_Rx_Stop, 15 UART_Rx_Width, 16 Parity_Set, 17 UART_Rx_LCK_En, 18 Baud_CLk_half, 19 UART_Rx_Data, 20 UART_Rx_Done, 21 UART_Rx_Error, 22 UART_Rx 23 ); 24 25 //=================================<端口>=========================== 26 //-- 物理端口 27 input clk; //时钟信号 28 input rst_n; //复位信号 29 input UART_Rx; //UART输入引脚 30 //-- 上级系统通信 31 input UART_Rx_En; //接收使能 32 input UART_Rx_Stop; //接收失能 33 input [3:0]UART_Rx_Width; //接收收据位宽 34 input [2:0]Parity_Set; //校验位设置 0:无校验 1:奇校验 35 // 2:偶校验 3:置1 4:置0 36 output reg UART_Rx_LCK_En; //使能接收波特率时钟信号 37 input Baud_CLk_half; //数据接收时钟 38 output reg [7:0]UART_Rx_Data; //接收到的数据 39 output reg UART_Rx_Done; //接收结束 40 output reg UART_Rx_Error; //校验失败 41 //-- 内部信号 42 reg Rx_state; //接收状态 43 reg [3:0]data_width; //待接收数据位宽寄存器 44 reg [2:0]Parity; //校验方式设置 45 reg [3:0]cnt; //接收BIT计数器 46 reg Parity_data; //接收校验值 47 reg Parity_cal; //计算的校验值 48 reg half_clk_r; //波特率时钟延迟一个系统时钟周期，采完值后作比较 49 reg wait_Rx_state; //等待接收状态 50 reg UART_Rx_r; //UART_Rx_r寄存器 51 //------------------------------------------------------------------- 52 //--序号01 功能描述：接收上级指令或数据 53 //------------------------------------------------------------------- 54 //--data_width 55 always@(posedge clk or negedge rst_n) 56 if(!rst_n) 57 data_width <= 4'd0; 58 else if(UART_Rx_En) 59 data_width <= UART_Rx_Width; 60 else 61 data_width <= data_width; 62 //--Parity 63 always@(posedge clk or negedge rst_n) 64 if(!rst_n) 65 Parity <= 3'd0; 66 else if(UART_Rx_En) 67 Parity <= Parity_Set; 68 else 69 Parity <= Parity; 70 //------------------------------------------------------------------- 71 //--序号02 功能描述：接收数据 72 //------------------------------------------------------------------- 73 //--UART_Rx寄存一个时钟周期 74 always@(posedge clk or negedge rst_n) 75 if(!rst_n) 76 UART_Rx_r <= 1'b0; 77 else 78 UART_Rx_r <= UART_Rx; 79 80 //--wait_Rx_state确定//只能在空闲状态才能发停止采集的指令了。。。 81 always@(posedge clk or negedge rst_n) 82 if(!rst_n) 83 wait_Rx_state <= 1'b0; 84 else if(UART_Rx_En) 85 wait_Rx_state <= 1'b1; 86 else if(UART_Rx_LCK_En) 87 wait_Rx_state <= 1'b0; 88 else if(UART_Rx_Done) 89 wait_Rx_state <= 1'b1; 90 else if(UART_Rx_Stop) 91 wait_Rx_state <= 1'b0; 92 else 93 wait_Rx_state <= wait_Rx_state; 94 95 //--时钟使能信号 96 always@(posedge clk or negedge rst_n) 97 if(!rst_n) 98 UART_Rx_LCK_En <= 1'b0; 99 else if(wait_Rx_state && !UART_Rx && UART_Rx_r) 100 UART_Rx_LCK_En <= 1'b1; 101 else 102 UART_Rx_LCK_En <= 1'b0; 103 104 //--Rx_state接收数据状态 105 always@(posedge clk or negedge rst_n) 106 if(!rst_n) 107 Rx_state <= 1'b0; 108 else if(UART_Rx_LCK_En) 109 Rx_state <= 1'b1; 110 else if(UART_Rx_Done) 111 Rx_state <= 1'b0; 112 else 113 Rx_state <= Rx_state; 114 //--接收数据计数器 115 always@(posedge clk or negedge rst_n) 116 if(!rst_n) 117 cnt <= 4'd0; 118 else if(Rx_state)begin 119 if(Baud_CLk_half) 120 cnt <= cnt + 1'b1; 121 else 122 cnt <= cnt; 123 end 124 else 125 cnt <= 4'd0; 126 //--接收数据位 127 always@(posedge clk or negedge rst_n) 128 if(!rst_n) 129 UART_Rx_Data <= 8'd0; 130 else if(Rx_state)begin 131 if( Baud_CLk_half && (cnt > 1'b0)&&(cnt <= data_width) ) 132 UART_Rx_Data <= {UART_Rx,UART_Rx_Data[7:1]}; 133 else if((!Parity && Baud_CLk_half && cnt == data_width) || (Parity && half_clk_r && cnt == (data_width + 2'd2))) 134 UART_Rx_Data <= UART_Rx_Data >> (5'd8 - data_width); 135 else 136 UART_Rx_Data <= UART_Rx_Data; 137 end 138 else 139 UART_Rx_Data <= 8'd0; 140 //--接收校验位 141 always@(posedge clk or negedge rst_n) 142 if(!rst_n) 143 Parity_data <= 1'b0; 144 else if(Rx_state)begin 145 if( Baud_CLk_half && (cnt > data_width) && Parity) 146 Parity_data <= UART_Rx ; 147 else 148 Parity_data <= Parity_data; 149 end 150 else 151 Parity_data <= 1'b0; 152 //--计算校验位 153 always@(posedge clk or negedge rst_n) 154 if(!rst_n) 155 Parity_cal <= 1'b0; 156 else if(Rx_state)begin 157 if( Baud_CLk_half && (cnt > 1'b0)&&(cnt <= data_width) && ((Parity == 3'd2)|| (Parity == 3'd1)) ) 158 Parity_cal <= UART_Rx + Parity_cal; 159 else if(Baud_CLk_half && (Parity == 3'd1) &&(cnt == data_width + 1'b1) ) 160 Parity_cal <= ~Parity_cal; 161 else if(Parity == 3'd3) 162 Parity_cal <= 1'b1; 163 else if(Parity == 3'd4) 164 Parity_cal <= 1'b0; 165 else 166 Parity_cal <= Parity_cal; 167 end 168 else 169 Parity_cal <= 1'b0; 170 //--延迟一个系统时钟周期的波特率时钟 171 always@(posedge clk or negedge rst_n) 172 if(!rst_n) 173 half_clk_r <= 1'b0; 174 else 175 half_clk_r <= Baud_CLk_half; 176 //--接收结束使能 177 always@(posedge clk or negedge rst_n) 178 if(!rst_n) 179 UART_Rx_Done <= 1'b0; 180 else if(!Parity && Baud_CLk_half && cnt == data_width ) 181 UART_Rx_Done <= 1'b1; 182 else if(Parity && half_clk_r && cnt == (data_width + 2'd2) ) 183 UART_Rx_Done <= 1'b1; 184 else 185 UART_Rx_Done <= 1'b0; 186 //--校验失败使能 187 always@(posedge clk or negedge rst_n) 188 if(!rst_n) 189 UART_Rx_Error <= 1'b0; 190 else if(Parity && cnt == (data_width + 2'd2) && half_clk_r )begin 191 if(((Parity == 3'd1)||(Parity == 3'd2)) && Parity_cal != Parity_data ) 192 UART_Rx_Error <= 1'b1; 193 else if(Parity == 3'd3 && !Parity_data) 194 UART_Rx_Error <= 1'b1; 195 else if(Parity == 3'd4 && Parity_data) 196 UART_Rx_Error <= 1'b1; 197 else 198 UART_Rx_Error <= 1'b0; 199 end 200 else 201 UART_Rx_Error <= 1'b0; 202 203 endmodule
4、控制模块
1 /*************************************************** 2 * Module Name : UART_CTL_module 3 * Engineer : 王小虎 4 * Target Device : EP4CE10F17C8 5 * Tool versions : Quartus II 13.0 6 * Create Date : 2019 7 * Revision : v1.0 8 * Description : 9 **************************************************/ 10 module UART_CTL_module( 11 clk, 12 rst_n, 13 UART_Tx_En, 14 UART_Tx_Data, 15 UART_Tx_Width, 16 UART_Tx_Baud_Set, 17 UART_Tx_STOP_Bit, 18 UART_Tx_Parity_Set, 19 UART_Tx_Done, 20 UART_Rx_En, 21 UART_Rx_Stop, 22 UART_Rx_Width, 23 UART_Rx_Baud_Set, 24 UART_Rx_Parity_Set, 25 UART_Rx_Data, 26 UART_Rx_Done, 27 UART_Rx_Error, 28 UART_Tx, 29 UART_Rx 30 ); 31 32 //=================================<端口>=========================== 33 //-- 物理端口 34 input clk; //时钟信号 35 input rst_n; //复位信号 36 output UART_Tx; //UART输出信号 37 input UART_Rx; //UART输入引脚 38 //-- 上级系统通信 39 input UART_Tx_En; //UART_Tx发送使能 40 input [7:0]UART_Tx_Data; //待发送数据 41 input [3:0]UART_Tx_Width; //待发送数据位宽 42 input [3:0]UART_Tx_Baud_Set; //发送波特率选择 43 input [1:0]UART_Tx_STOP_Bit; //停止位位宽设置 00:1 01:1.5 10:2 44 input [2:0]UART_Tx_Parity_Set; //校验位设置 0:无校验 1:奇校验 45 // 2:偶校验 3:置1 4:置0 46 output UART_Tx_Done; //单次发送结束 47 input UART_Rx_En; //接收使能 48 input UART_Rx_Stop; //接收失能 49 input [3:0]UART_Rx_Width; //接收收据位宽 50 input [2:0]UART_Rx_Parity_Set; //校验位设置 0:无校验 1:奇校验 51 // 2:偶校验 3:置1 4:置0 52 input [3:0]UART_Rx_Baud_Set; //发送波特率选择 53 output [7:0]UART_Rx_Data; //接收到的数据 54 output UART_Rx_Done; //接收结束 55 output UART_Rx_Error; //校验失败 56 57 //-- 下级系统通信 58 wire UART_Rx_LCK_En; //使能接收波特率时钟信号 59 wire UART_Tx_Baud_CLk; //输出波特率时钟 60 wire UART_Tx_Baud_CLk_half; //输出加倍波特率时钟 61 wire UART_Rx_Baud_CLk_half; //输出加倍波特率时钟 62 //-- 内部信号 63 64 65 //------------------------------------------------------------------- 66 //--序号01 功能描述： 67 //------------------------------------------------------------------- 68 69 //------------------------------------------------------------------- 70 //--序号02 功能描述： 71 //------------------------------------------------------------------- 72 73 74 //------------------------------------------------------------------- 75 //-- 模块例化 76 //------------------------------------------------------------------- 77 UART_Tx_module Tx_module( 78 .clk(clk), 79 .rst_n(rst_n), 80 .UART_Tx_En(UART_Tx_En), 81 .UART_Tx_Data(UART_Tx_Data), 82 .UART_Tx_Width(UART_Tx_Width), 83 .STOP_Bit(UART_Tx_STOP_Bit), 84 .Parity_Set(UART_Tx_Parity_Set), 85 .Baud_CLk(UART_Tx_Baud_CLk), 86 .Baud_CLk_half(UART_Tx_Baud_CLk_half), 87 .UART_Tx_Done(UART_Tx_Done), 88 .UART_Tx(UART_Tx) 89 ); 90 UART_Baud_CLK Tx_Baud_CLK( 91 .clk(clk), 92 .rst_n(rst_n), 93 .UART_En(UART_Tx_En), 94 .UART_Done(UART_Tx_Done), 95 .Baud_Set(UART_Tx_Baud_Set), 96 .Baud_CLk(UART_Tx_Baud_CLk), 97 .Baud_CLk_half(UART_Tx_Baud_CLk_half) 98 ); 99 UART_Rx_module Rx_module( 100 .clk(clk), 101 .rst_n(rst_n), 102 .UART_Rx_En(UART_Rx_En), 103 .UART_Rx_Stop(UART_Rx_Stop), 104 .UART_Rx_Width(UART_Rx_Width), 105 .Parity_Set(UART_Rx_Parity_Set), 106 .UART_Rx_LCK_En(UART_Rx_LCK_En), 107 .Baud_CLk_half(UART_Rx_Baud_CLk_half), 108 .UART_Rx_Data(UART_Rx_Data), 109 .UART_Rx_Done(UART_Rx_Done), 110 .UART_Rx_Error(UART_Rx_Error), 111 .UART_Rx(UART_Rx) 112 ); 113 114 UART_Baud_CLK Rx_Baud_CLK( 115 .clk(clk), 116 .rst_n(rst_n), 117 .UART_En(UART_Rx_LCK_En), 118 .UART_Done(UART_Rx_Done), 119 .Baud_Set(UART_Rx_Baud_Set), 120 .Baud_CLk(), 121 .Baud_CLk_half(UART_Rx_Baud_CLk_half) 122 ); 123 endmodule