The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
The LEON2 is based on an AMBA AHB/APB bus architecture, so new modules can easily be added to extend its functionality.
Advanced Microcontroller Bus Architecture. AMBA was introduced by ARM in 1996. The first AMBA buses were Advanced System Bus (ASB) and Advanced Peripheral Bus (APB). In its second version, AMBA 2 in 1999, ARM added AMBA High-performance Bus (AHB) that is a single clock-edge protocol.
The LEON2-FT design is an extension of the basic LEON2 model including advanced fault-tolerance features to withstand arbitrary single-event upset (SEU) errors without loss of data. The fault-tolerance is provided at design (VHDL) level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools. Atmel has manufactured an ASIC version of the LEON2-FT in the ATH18RHA rad hard process, available through their catalogue as part number AT697F.
Microchip已经收购Atmel，Mircochip的单片机为PIC，Atmel的单片机为AVR，两者结合为了更好的应对ARM的竞争。
April 4, 2016 – Microchip Technology Incorporated (NASDAQ: MCHP), a leading provider of microcontroller, mixed-signal, analog and flash-IP solutions, today announced that it has completed its acquisition of Atmel Corporation.
Microchip/Atmel have the theopportunity to combine the best of the AVR and PIC worlds into an awesomemicrocontroller platform. Despite the growing popularity and decreasingcost of powerful 32-bit ARM chips, there are still plenty of applicationswhere 8 bits are all you need.
The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the IEEE-1754 (SPARC V8) architecture. The LEON3 is an extension to the LEON2 processor, featuring a 7-stage pipeline (vs the 5-stage pipeline of the LEON2), and supporting both asymmetric and symmetric multiprocessing (AMP/SMP). Up to 16 CPU can be used in a multiprocessing configuration. 多核
The LEON4 is the latest implementation of the SPARC V8 architecture by Aeroflex Gaisler, in the form of a synthesizable VHDL model of a 32-bit microprocessor. As was the case with the previous LEON models, the LEON4 is also highly configurable, and particularly suitable for system-on-chip (SoC) designs. The LEON4 extends the LEON3 model with support for an optional Level-2 (L2) cache, a pipeline with 64-bit internal load/store data paths, and an AMBA interface of either 64- or 128-bits. Branch prediction, 1-cycle load latency and a 32x32 multiplier results in a performance of 1.7 DMIPS/MHz, or 2.1 CoreMark/MHz.
