Xilinx FPGA BRAM 实践笔记（一）

本笔记实现的功能是：

通过BRAM中的16位位宽的数据，控制16个LED等闪烁。

BRAM的配置为single dual BRAM

16位位宽，深度也是16位

初始化文件 mem.coe

memory_initialization_radix=16;
memory_initialization_vector=fff0 ff0f f0ff 0fff fff0 ff0f f0ff 0fff fff0 ff0f f0ff 0fff fff0 ff0f f0ff 0fff;

top文件 ov5640_top.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2019/05/04 21:38:16
// Design Name:
// Module Name: ov5640_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module ov5640_top(
input clk,
input rst_n,
input sw0,
output reg[15:0]led
);

reg ena;

reg enb;

reg wea;

reg[3:0] addra;

reg[3:0] addrb;

reg[15:0] dina;

// blk_mem_gen_0 outputs

wire[15:0] douta;

wire[15:0] doutb;

/**************简单双端口RAM A进B出**************/

blk_mem_gen_0 blk_mem_gen_m0

(

.clka(clk), //BRAM 输入时钟信号

.ena(ena), //BRAM 时钟使能信号

.wea(wea), //写使能信号

.addra(addra), //地址信号

.dina(dina), //数据输入接口写入

.clkb(clk), //BRAM 输入时钟信号

.enb(enb), //BRAM 时钟使能信号

.addrb(addrb), //地址信号

.doutb(doutb)

);

initial
begin
ena = 0;

enb = 0;

wea = 0;

addra = 0;

addrb = 0;

dina = 0;
end

reg [31:0] cnt = 32'h0;

always @(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt = 32'h0;
else if(cnt == 32'h2fa_f080)
begin
cnt <= 32'h0;
if(addrb == 4'h3)
addrb = 4'h00;
else
addrb <= addrb + 1;
end
else
begin
cnt <= cnt+1;
// addrb = 1;
enb <= 1;
led <= doutb;
end
end

endmodule

约束文件

set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports clk]
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports rst_n]
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports sw0]

set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN G4 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN G3 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
set_property -dict {PACKAGE_PIN J4 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
set_property -dict {PACKAGE_PIN H4 IOSTANDARD LVCMOS33} [get_ports {led[4]}]
set_property -dict {PACKAGE_PIN J3 IOSTANDARD LVCMOS33} [get_ports {led[5]}]
set_property -dict {PACKAGE_PIN J2 IOSTANDARD LVCMOS33} [get_ports {led[6]}]
set_property -dict {PACKAGE_PIN K2 IOSTANDARD LVCMOS33} [get_ports {led[7]}]
set_property -dict {PACKAGE_PIN K1 IOSTANDARD LVCMOS33} [get_ports {led[8]}]
set_property -dict {PACKAGE_PIN H6 IOSTANDARD LVCMOS33} [get_ports {led[9]}]
set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports {led[10]}]
set_property -dict {PACKAGE_PIN J5 IOSTANDARD LVCMOS33} [get_ports {led[11]}]
set_property -dict {PACKAGE_PIN K6 IOSTANDARD LVCMOS33} [get_ports {led[12]}]
set_property -dict {PACKAGE_PIN L1 IOSTANDARD LVCMOS33} [get_ports {led[13]}]
set_property -dict {PACKAGE_PIN M1 IOSTANDARD LVCMOS33} [get_ports {led[14]}]
set_property -dict {PACKAGE_PIN K3 IOSTANDARD LVCMOS33} [get_ports {led[15]}]

Xilinx FPGA BRAM 实践笔记（一）

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