AXI的Register Slice 结构及代码

AXI Register Slice可以配置为以下4种情况

1.Forward Registered – Pipeline the forward control path and the corresponding AXI channel payload.

2.Backward Registered – Pipeline the backward control path only.

3.Fully Registered – Pipeline the forward control path, the corresponding AXI channel payload, and the backward control path.

4.Pass Through Mode – All AXI channel signals are directly connected from input to output.

一.前向Register

其中payload可以是cmd或data，valid可以是cmd valid也可以是data valid

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'd0)
        valid_dst <= 1'd0;
    else if (valid_src == 1'd1)
        valid_dst <= #`DLY 1'd1;
    else if (ready_dst == 1'd1)
        valid_dst <= #`DLY 1'd0;
end

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'd0)
        payload_dst <= 'd0;
    else if (valid_src == 1'd1 && ready_src == 1'd1)
        payload_dst <= #`DLY payload_src;
end

ready_src = (~valid_dst) | ready_dst

二.后向Register

代码如下：

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'd0)
        valid_tmp0 <= 1'd0;
    else if (valid_src == 1'd1 && ready_dst == 1'd0 && valid_tmp0 == 1'd0)
        valid_tmp0 <= #`DLY 1'd1;
    else if (ready_dst == 1'd1)
        valid_tmp0 <= #`DLY 1'd0;
end

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'd0)
        payload_tmp0 <= 'd0;
    else if (valid_src == 1'd1 && ready_dst == 1'd0 && valid_tmp0 == 1'd0)
        payload_tmp0 <= #`DLY payload_src;
end

assign payload_dst = (valid_tmp0 == 1'd1) ? payload_tmp0 : payload_src;

always @(posedge clk or negedge rst_n) begin
    if (rst_n == 1'd0)
        ready_src <= 1'd0;
    else
        ready_src <= #`DLY ready_dst;
end

三.双向Register

可以用乒乓register的形式 payload的非空信号做valid_dst；payload的非满信号做ready_src

四.pass through

这种情况就是不使用register