xilinx vivado的Combinatorial Loop Alert问题

[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this DRC can be bypassed by acknowledging the condition and setting the following XDC constraint on any one of the nets in the loop: 'set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets <myHier/myNet>]'. One net in the loop is cycling_v1_i/mt100ht_vienna_v2_0/inst/bram1_din[0]. Please evaluate your design. The cells in the loop are: cycling_v1_i/mt100ht_vienna_v2_0/inst/bram1_din_inferred_i_32.

解决办法是写约束条件：set_property ALLOW_COMBINATORIAL_LOOPS TRUE [get_nets cycling_v1_i/mt100ht_vienna_v2_0/inst/bram1_din[0]];