; ========================== ; zero page get address ; ========================== __zrp_get: movzx eax, byt[ebx+1] mov byt[__addr8_r], al add wot[__pc], 1 ret ; ========================== ; zero page x get address ; ========================== __zrpx_get: movzx eax, byt[ebx+1] add al, byt[__x] mov byt[__addr8_r], al add wot[__pc], 1 ret ; ========================== ; zero page y get address ; ========================== __zrpy_get: movzx eax, byt[ebx+1] add al, byt[__y] mov byt[__addr8_r], al add wot[__pc], 1 ret ; ========================== ; abs get address ; ========================== __abs_get: movzx eax, wot[ebx+1] mov wot[__addr16_r], ax add wot[__pc], 2 ret ; ========================== ; abs x get address ; ========================== __absx_get: movzx eax, wot[ebx+1] movzx ecx, byt[__x] mov wot[__addr16_t], ax add ecx, eax mov wot[__addr16_r], cx add wot[__pc], 2 ret ; ========================== ; abs y get address ; ========================== __absy_get: movzx eax, wot[ebx+1] movzx ecx, byt[__y] mov wot[__addr16_t], ax add ecx, eax mov wot[__addr16_r], cx add wot[__pc], 2 ret ; ========================== ; x indirect get address ; ========================== __xid_get: movzx eax, byt[ebx+1] add al, byt[__x] movzx eax, wot[ram+eax] mov wot[__addr16_r], ax add wot[__pc], 1 ret ; ========================== ; indirect y get address ; ========================== __idy_get: movzx eax, byt[ebx+1] movzx eax, wot[ram+eax] movzx ecx, byt[__y] mov wot[__addr16_t], ax add ecx, eax mov wot[__addr16_r], cx add wot[__pc], 1 ret ; ========================== ; immed read ; ========================== __imm_r: mov al, byt[ebx+1] mov byt[__val8_t], al add wot[__pc], 1 ret ; ========================== ; zero page read ; ========================== __zrp_r: movzx eax, byt[ebx+1] mov byt[__addr8_r], al mov al, byt[ram+eax] mov byt[__val8_t], al add wot[__pc], 1 ret ; ========================== ; zero page x read ; ========================== __zrpx_r: movzx eax, byt[ebx+1] add al, byt[__x] mov byt[__addr8_r], al mov al, byt[ram+eax] add wot[__pc], 1 mov byt[__val8_t], al ret ; ========================== ; zero page y read ; ========================== __zrpy_r: movzx eax, byt[ebx+1] add al, byt[__y] mov byt[__addr8_r], al mov al, byt[ram+eax] add wot[__pc], 1 mov byt[__val8_t], al ret ; ========================== ; abs read ; ========================== __abs_r: movzx eax, wot[ebx+1] mov wot[__addr16_r], ax push eax call readmem@4 add wot[__pc], 2 mov byt[__val8_t], al ret ; ========================== ; abs x read ; ========================== __absx_r: movzx eax, wot[ebx+1] movzx ecx, byt[__x] mov wot[__addr16_t], ax add cx, ax mov wot[__addr16_r], cx push ecx call readmem@4 add wot[__pc], 2 mov byt[__val8_t], al ret ; ========================== ; abs y read ; ========================== __absy_r: movzx eax, wot[ebx+1] movzx ecx, byt[__y] mov wot[__addr16_t], ax add cx, ax mov wot[__addr16_r], cx push ecx call readmem@4 add wot[__pc], 2 mov byt[__val8_t], al ret ; ========================== ; x indirect read ; ========================== __xid_r: movzx eax, byt[ebx+1] add al, byt[__x] movzx eax, wot[ram+eax] mov wot[__addr16_r], ax push eax call readmem@4 add wot[__pc], 1 mov byt[__val8_t], al ret ; ========================== ; indirect y read ; ========================== __idy_r: movzx eax, byt[ebx+1] movzx eax, wot[ram+eax] movzx ecx, byt[__y] mov wot[__addr16_t], ax add cx, ax mov wot[__addr16_r], cx push ecx add wot[__pc], 1 call readmem@4 mov byt[__val8_t], al ret ; ========================== ; addr 8 write ; ========================== __zrp_w: __zrpx_w: __zrpy_w: movzx eax, byt[__addr8_r] mov cl, byt[__val8_t] mov byt[ram+eax], cl ret ; ========================== ; addr 16 write ; ========================== __abs_w: __absx_w: __absy_w: __xid_w: __idy_w: movzx eax, wot[__addr16_r] movzx ecx, byt[__val8_t] push ecx push eax call writemem@8 ret __chk_cross_page: mov al, byt[__addr16_r+1] mov cl, byt[__addr16_t+1] ; get high 8 bit ... cmp al, cl je __no_cross inc wot[curCnt] ret __no_cross: ret
; =================== ; ADC ; =================== IF 0 __adc: movzx eax, byt[__a] ; load reg_a movzx ebx, byt[__p] ; load psw movzx edx, byt[__val8_t] ; load val mov esi, ebx ; save C flag ... and esi, 1 ; only C flag mov di, dx add di, ax mov cx, di add cx, si ; with C flag ; ax <- reg_a ; dx <- val ; cx <- temp16 mov byt[__a], cl ; write __a xor dl, al ; arg1 xor al, cl ; arg2 xor dl, 080h and al, dl and al, 080h shr al, 1 or bl, al movzx eax, cl cmp cx, 0FFh ja __set_c_flag or ebx, dwot[zn_t+eax*4] mov byt[__p], bl ret __set_c_flag: or ebx, 1 or ebx, dwot[zn_t+eax*4] mov byt[__p], bl ret ELSE __adc: movzx eax, byt[__a] ; load reg_a movzx ebx, byt[__p] ; load psw movzx edx, byt[__val8_t] ; load val and ebx, 00111101b ; save c flag ... shr ebx, 1 ; C into x86's cpu psw adc al, dl seto dl ; set over flag rcl bl, 1 shl dl, 6 or bl, dl or ebx, dwot[zn_t+eax*4] mov byt[__p], bl mov byt[__a], al ret ENDIF ; =================== ; SBC ; =================== __sbc: movzx eax, byt[__a] ; load reg_a movzx ebx, byt[__p] ; load psw movzx edx, byt[__val8_t] ; load val mov esi, ebx ; save C flag ... and ebx, 00111100b and esi, 1 ; only C flag xor esi, 1 movzx edi, al ; save reg_a sub edi, esi ; with C flag ... sub di, dx ; di <- temp16 xor dl, al ; val ^= reg_a xor ax, di ; and dl, al ; and dl, 080h shr dl, 1 or bl, dl ; reset v flag mov ax, di mov byt[__a], al cmp di, 0FFh ja __no_set_c or ebx, 1 or ebx, dwot[zn_t+eax*4] mov byt[__p], bl ret __no_set_c: or ebx, dwot[zn_t+eax*4] mov byt[__p], bl ret ; =================== ; ORA ; =================== __ora: movzx eax, byt[__a] mov cl, byt[__p] mov dl, byt[__val8_t] and ecx, 01111101b or al, dl ; ORA opr or ecx, dwot[zn_t+eax*4] mov byt[__a], al mov byt[__p], cl ret ; =================== ; AND ; =================== __and: movzx eax, byt[__a] mov cl, byt[__p] mov dl, byt[__val8_t] and ecx, 01111101b and al, dl ; AND opr or ecx, dwot[zn_t+eax*4] mov byt[__a], al mov byt[__p], cl ret ; =================== ; EOR ; =================== __eor: movzx eax, byt[__a] mov cl, byt[__p] mov dl, byt[__val8_t] and ecx, 01111101b xor al, dl ; EOR opr or ecx, dwot[zn_t+eax*4] mov byt[__a], al mov byt[__p], cl ret ; =================== ; STA ; =================== __sta: mov al, byt[__a] mov byt[__val8_t], al ret ; =================== ; LDA ; =================== __lda: movzx eax, byt[__p] and eax, 01111101b movzx ecx, byt[__val8_t] or eax, dwot[zn_t+ecx*4] mov byt[__p], al mov byt[__a], cl ret ; =================== ; STX ; =================== __stx: mov al, byt[__x] mov byt[__val8_t], al ret ; =================== ; LDX ; =================== __ldx: movzx eax, byt[__p] and eax, 01111101b movzx ecx, byt[__val8_t] or eax, dwot[zn_t+ecx*4] mov byt[__p], al mov byt[__x], cl ret ; =================== ; STY ; =================== __sty: mov al, byt[__y] mov byt[__val8_t], al ret ; =================== ; LDY ; =================== __ldy: movzx eax, byt[__p] and eax, 01111101b movzx ecx, byt[__val8_t] or eax, dwot[zn_t+ecx*4] mov byt[__p], al mov byt[__y], cl ret ; =================== ; CMP ; =================== __cmp: movzx eax, byt[__p] movzx edx, byt[__a] and eax, 01111100b movzx ecx, byt[__val8_t] sub dx, cx movzx ebx, dl and dx, 08000h shr dx, 15 xor dx, 1 or eax, edx ; reset C flag ... or eax, dwot[zn_t+ebx*4] mov byt[__p], al ret ; =================== ; CPX ; =================== __cpx: movzx eax, byt[__p] movzx edx, byt[__x] and eax, 01111100b movzx ecx, byt[__val8_t] sub dx, cx movzx ebx, dl and dx, 08000h shr dx, 15 xor dx, 1 or eax, edx ; reset C flag ... or eax, dwot[zn_t+ebx*4] mov byt[__p], al ret ; =================== ; CPY ; =================== __cpy: movzx eax, byt[__p] movzx edx, byt[__y] and eax, 01111100b movzx ecx, byt[__val8_t] sub dx, cx movzx ebx, dl and dx, 08000h shr dx, 15 xor dx, 1 or eax, edx ; reset C flag ... or eax, dwot[zn_t+ebx*4] mov byt[__p], al ret ; =================== ; DEC ; =================== __dec: movzx eax, byt[__p] movzx ecx, byt[__val8_t] and eax, 07Dh dec cl or eax, dwot[zn_t+ecx*4] mov byt[__val8_t], cl mov byt[__p], al ret ; =================== ; DEX ; =================== __dex: movzx eax, byt[__p] movzx ecx, byt[__x] and eax, 07Dh dec cl or eax, dwot[zn_t+ecx*4] mov byt[__x], cl mov byt[__p], al ret ; =================== ; DEY ; =================== __dey: movzx eax, byt[__p] movzx ecx, byt[__y] and eax, 07Dh dec cl or eax, dwot[zn_t+ecx*4] mov byt[__y], cl mov byt[__p], al ret ; =================== ; INC ; =================== __inc: movzx eax, byt[__p] movzx ecx, byt[__val8_t] and eax, 07Dh inc cl or eax, dwot[zn_t+ecx*4] mov byt[__val8_t], cl mov byt[__p], al ret ; =================== ; INX ; =================== __inx: movzx eax, byt[__p] movzx ecx, byt[__x] and eax, 07Dh inc cl or eax, dwot[zn_t+ecx*4] mov byt[__x], cl mov byt[__p], al ret ; =================== ; INY ; =================== __iny: movzx eax, byt[__p] movzx ecx, byt[__y] and eax, 07Dh inc cl or eax, dwot[zn_t+ecx*4] mov byt[__y], cl mov byt[__p], al ret ; =================== ; BIT ; =================== __bit: movzx eax, byt[__p] and eax, 00111101b movzx ecx, byt[__val8_t] mov edx, ecx and ecx, 0C0h or eax, ecx ; reset n-v flag and dl, byt[__a] sete cl lea eax, [eax+ecx*2] ; reset z flag mov byt[__p], al ret ; =================== ; ASL_A ; =================== __asl_a: movzx eax, byt[__a] movzx ecx, byt[__p] and ecx, 01111100b test eax, 080h je __no_c_flag or ecx, 1 shl al, 1 mov byt[__a], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret __no_c_flag: shl al, 1 mov byt[__a], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret ; =================== ; ASL ; =================== __asl: movzx eax, byt[__val8_t] movzx ecx, byt[__p] and ecx, 01111100b test eax, 080h je __no_c_flag_s or ecx, 1 shl al, 1 mov byt[__val8_t], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret __no_c_flag_s: shl al, 1 mov byt[__val8_t], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret ; =================== ; LSR_A ; =================== __lsr_a: movzx eax, byt[__a] movzx ecx, byt[__p] and ecx, 01111100b test eax, 01h je ___no_c_flag or ecx, 1 shr al, 1 mov byt[__a], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret ___no_c_flag: shr al, 1 mov byt[__a], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret ; =================== ; LSR ; =================== __lsr: movzx eax, byt[__val8_t] movzx ecx, byt[__p] and ecx, 01111100b test eax, 01h je ___no_c_flag_s or ecx, 1 shr al, 1 mov byt[__val8_t], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret ___no_c_flag_s: shr al, 1 mov byt[__val8_t], al or ecx, dwot[zn_t+eax*4] mov byt[__p], cl ret ; =================== ; ROL_A ; =================== __rol_a: movzx eax, byt[__a] movzx ecx, byt[__p] mov edx, ecx and ecx, 01111100b test eax, 080h ; jne __vcpt test edx, 01h je __vnpn shl al, 1 or al, 1 jmp __shift_final_a __vnpn: shl al, 1 jmp __shift_final_a __vcpt: test edx, 01h je __vcpn or ecx, 1 shl al, 1 or al, 1 jmp __shift_final_a __vcpn: or ecx, 1 shl al, 1 jmp __shift_final_a __shift_final_a: or ecx, dwot[zn_t+eax*4] mov byt[__p], cl mov byt[__a], al ret __shift_final: or ecx, dwot[zn_t+eax*4] mov byt[__p], cl mov byt[__val8_t], al ret ; =================== ; ROL ; =================== __rol: movzx eax, byt[__val8_t] movzx ecx, byt[__p] mov edx, ecx and ecx, 01111100b test eax, 080h ; jne __vcpt_s test edx, 01h je __vnpn_s shl al, 1 or al, 1 jmp __shift_final __vnpn_s: shl al, 1 jmp __shift_final __vcpt_s: test edx, 01h je __vcpn_s or ecx, 1 shl al, 1 or al, 1 jmp __shift_final __vcpn_s: or ecx, 1 shl al, 1 jmp __shift_final ; =================== ; ROR_A ; =================== __ror_a: movzx eax, byt[__a] movzx ecx, byt[__p] mov edx, ecx and ecx, 01111100b test eax, 01h ; jne ___vcpt test edx, 01h je ___vnpn shr al, 1 or al, 080h jmp __shift_final_a ___vnpn: shr al, 1 jmp __shift_final_a ___vcpt: test edx, 01h je ___vcpn or ecx, 1 shr al, 1 or al, 080h jmp __shift_final_a ___vcpn: or ecx, 1 shr al, 1 jmp __shift_final_a ; =================== ; ROR ; =================== __ror: movzx eax, byt[__val8_t] movzx ecx, byt[__p] mov edx, ecx and ecx, 01111100b test eax, 01h ; jne ___vcpt_s test edx, 01h je ___vnpn_s shr al, 1 or al, 080h jmp __shift_final ___vnpn_s: shr al, 1 jmp __shift_final ___vcpt_s: test edx, 01h je ___vcpn_s or ecx, 1 shr al, 1 or al, 080h jmp __shift_final ___vcpn_s: or ecx, 1 shr al, 1 jmp __shift_final ; =================== ; JMP ; =================== OP4C: ; jmp abs movzx eax, wot[ebx+1] mov wot[__pc], ax jmp peek_int OP6C: ; inDirect JMP expection crossing page boundaries in 6C ; NES JMP(only 6C)'s BUG: if addr is 0x--FF(Crossing Page) IP's High Bit Will Not Add ; ; $2500: 33 ; $25FF: 76 ; $2600: 89 ; $7574: 6C FF 25 ; IP <- $7574 ; ; Step1-> Get IP's Low Bit FF ; Step2-> Get IP's High Bit 25 ; $(25FF-2600) will crossing page so low bit is $25FF High Bit is $2500 ; jmp to $3376 ... movzx ebx, wot[ebx+1] ; get addr cmp bl, 0FFh ; crossing page ? jne ncropage push ebx call readmem@4 sub ebx, 0FFh push ebx mov bl, al call readmem@4 mov bh, al mov wot[__pc], bx jmp peek_int align 16 ncropage: push ebx call readmemw add esp, 4 mov wot[__pc], ax jmp peek_int ; =================== ; JSR ; =================== OP20: ; JSR mov dx, wot[ebx+1] mov cx, wot[__pc] movzx eax, byt[__s] inc cx mov wot[ram+0100h+eax-1], cx sub eax, 2 mov byt[__s], al mov wot[__pc], dx jmp peek_int ; =================== ; RTI ; =================== OP40: ; RTI movzx eax, byt[__s] add eax, 3 mov bl, byt[eax+ram+0100h-2] ; flag mov cx, wot[eax+ram+0100h-1] ; pc or bl, R_FLAG mov wot[__pc], cx mov byt[__s], al mov byt[__p], bl jmp peek_int ; =================== ; RTS ; =================== OP60: ; RTS movzx eax, byt[__s] add eax, 2 mov bx, wot[eax+ram+0100h-1] inc bx mov wot[__pc], bx mov byt[__s], al jmp peek_int ; =================== ; JCC ; =================== ; d7 - d0: N V R B D I Z C OP90: ; BCC test byt[__p], 00000001b je fhit jmp fnhit OPD0: ; BNE test byt[__p], 00000010b je fhit jmp fnhit OP10: ; BPL test byt[__p], 10000000b je fhit jmp fnhit OP50: ; BVC test byt[__p], 01000000b je fhit jmp fnhit OPB0: ; BCS test byt[__p], 00000001b jne fhit jmp fnhit OPF0: ; BEQ test byt[__p], 00000010b jne fhit jmp fnhit OP30: ; BMI test byt[__p], 10000000b jne fhit jmp fnhit OP70: ; BVS test byt[__p], 01000000b jne fhit jmp fnhit align 16 fhit: movzx eax, wot[__pc] inc ax movsx ecx, byt[ebx+1] add ax, cx mov wot[__pc], ax add dwot[curCnt], 1 ; hit 3 cycles ... jmp peek_int align 16 fnhit: inc wot[__pc] ; add dwot[curCnt], 2 ; nohit 2 cycles ... jmp peek_int ; =================== ; REG to REG ; =================== OPAA: ; X = A movzx eax, byt [__a] mov byt[__x], al jmp regt_main OP8A: ; A = X movzx eax, byt [__x] mov byt[__a], al jmp regt_main OPA8: ; Y = A movzx eax, byt [__a] mov byt[__y], al jmp regt_main OP98: ; A = Y movzx eax, byt [__y] mov byt[__a], al jmp regt_main OPBA: ; X = S movzx eax, byt [__s] mov byt[__x], al jmp regt_main OP9A: ; S = X mov al, byt [__x] mov byt[__s], al jmp peek_int align 16 regt_main: mov cl, byt[__p] and cl, 07Dh ; clr z-n or ecx, dwot[zn_t+eax*4] mov byt[__p], cl jmp peek_int ; d7 - d0: N V R B D I Z C IF 1 OP18: ; CLC 0001 index:0 and byt[__p], 11111110b jmp fret OPD8: ; CLD 1101 index:6 and byt[__p], 11110111b jmp fret OP58: ; CLI 1001 index:4 and byt[__p], 11111011b jmp fret OPB8: ; CLV 1011 index:5 and byt[__p], 10111111b jmp fret OP38: ; SEC 0011 index:1 or byt[__p], 00000001b jmp fret OPF8: ; SED 1111 index:7 or byt[__p], 00001000b jmp fret OP78: ; SEI 0111 index:3 or byt[__p], 00000100b fret: ; sub dwot[surv_c], 2 jmp peek_int ELSE OP18: ; CLC 0001 index:0 OPD8: ; CLD 1101 index:6 OP58: ; CLI 1001 index:4 OPB8: ; CLV 1011 index:5 OP38: ; SEC 0011 index:1 OPF8: ; SED 1111 index:7 OP78: ; SEI 0111 index:3 mov cl, byt[__p] shr al, 5 mov dl, byt[psw_t+eax] mov bl, byt[psw_t+eax+8] and cl, dl xor cl, bl mov byt[__p], cl ; sub dwot[surv_c], 2 jmp peek_int psw_t db 0FEh, 0FEh, 078h, 0FBh db 0FBh, 0BFh, 0F7h, 0F7h db 000h, 001h, 087h, 004h dd 000h, 000h, 000h, 008h ENDIF OP00: ; BRK OPEA: ; nop jmp peek_int ; PHA/PHP/PLA/PLP OP48: ; PHA movzx eax, byt[__a] movzx ecx, byt[__s] mov byt[ram+0100h+ecx], al ; ram+0100h <- A dec cl ; ram+0100hptr-- mov byt[__s], cl ; write back staclkptr jmp peek_int OP68: ; PLA movzx ecx, byt[__s] movzx ebx, byt [__p] inc cl and ebx, 07Dh movzx eax, byt [ecx+ram+0100h] mov byt[__a], al or ebx , dwot[zn_t+eax*4] mov byt[__p], bl mov byt[__s], cl jmp peek_int OP08: ; PHP movzx eax, byt[__p] movzx ecx, byt[__s] or eax, B_FLAG nop mov byt[ram+0100h+ecx], al dec ecx mov byt[__s], cl jmp peek_int OP28: ; PLP movzx ecx, byt[__s] inc cl movzx eax, byt [ecx+ram+0100h] or eax, R_FLAG mov byt[__p], al mov byt[__s], cl jmp peek_int
.686 ; create 32 bit code .mmx .xmm .model flat, stdcall ; 32 bit memory model option casemap :none ; case sensitive ; **************** nes cpu by XXXX ******************* ; - ml -c 2a03core.asm ; ******************* NES Interrupt *********************** NMI_VECTOR equ FFFAh ; nmi RES_VECTOR equ FFFCh ; reset IRQ_VECTOR equ FFFEh ; irq ; ******************* NES Interrupt Flags *********************** NMI_FLAG equ 1 ; nmi interrupt pending flag IRQ_FLAG equ 2 ; irq interrupt pending flag ; ******************** CPU Register Flags *********************** C_FLAG equ 01h ; 1: carry? Z_FLAG equ 02h ; 1: zero I_FLAG equ 04h ; 1: intterrupt enable D_FLAG equ 08h ; 1: dec mode nes did not use this mode B_FLAG equ 10h ; 1: software intterrupt flag R_FLAG equ 20h ; 1: this flag is reserved V_FLAG equ 40h ; 1: overflow flag N_FLAG equ 80h ; 1: negative flag INT_C equ 7 byt equ byte ptr wot equ word ptr dwot equ dword ptr ALIGNXMM equ align 16 ; ********************* extern symbols ************************** ; reg group extrn __a:far extrn __x:far extrn __y:far extrn __s:far extrn __p:far extrn __pc:far ; mem extrn ram:far ; extrn ram+0100h:far extrn cpuBanks:far ; cycles cnt extrn dma_c:far extrn rva_c:far extrn surv_c:far extrn line_c:far ; extra extrn optab:far extrn zn_t:far ; fun extrn readmem@4:proc extrn readmemw:proc extrn writemem@8:proc extrn updateREG@0:proc ; int pending extrn int_pending:far .data? curCnt dd ? curOus dd ? .data __addr8_r db 0 __addr16_t dw 0 __addr16_r dw 0 __val8_t db 0 .code _DoIRQ proc C option prologue:none, epilogue:none movzx eax, byt[__s] ; load s movzx ecx, byt[__p] ; load flag movzx edx, wot[__pc]; load pc mov wot[eax+ram+0100h-1], dx ; push pc into ram+0100h and ecx, 0EFh ; clr B flag mov byt[eax+ram+0100h-2], cl ; push psw into ram+0100h or ecx, I_FLAG ; set int disabled flag mov eax, dword ptr[surv_c] mov byt[__p], cl sub eax, INT_C mov ecx, dword ptr[cpuBanks+28] mov cx, wot[ecx+01FFEh] ; set irq addr mov wot[__pc], cx mov dword ptr[surv_c], eax ret _DoIRQ endp _DoNMI proc C option prologue:none, epilogue:none movzx eax, byt[__s] ; load s movzx ecx, byt[__p] ; load flag movzx edx, wot[__pc]; load pc mov wot[eax+ram+0100h-1], dx ; push pc into ram+0100h and ecx, 0EFh ; clr B flag mov byt[eax+ram+0100h-2], cl ; push psw into ram+0100h sub eax, 3 or ecx, I_FLAG ; set int disabled flag mov byt[__s], al mov eax, dword ptr[surv_c] mov byt __p, cl add dwot[curCnt], INT_C mov ecx, dwot[cpuBanks+28] mov cx, wot[ecx+01FFAh] ; set nmi addr mov wot[__pc], cx ret _DoNMI endp exec2a03 proc C option prologue:none, epilogue:none mov eax, dwot[esp+4] ; Load Remain Cycles mov dwot[curCnt], 0 ; clr cycles cnt ... push esi ; save old frame push edi ; save old frame push ebx ; save old frame main_loop: mov ecx, dwot[curCnt] mov eax, dwot[esp+16] cmp eax, ecx ; remain cmp curCnt ja _continue _ret: pop ebx pop edi pop esi mov eax, dwot[curCnt] ret ; DMA test _continue: mov edx, dwot[esp+16] ; load Remain Cycles again cmp dwot[dma_c], 0 ja dma_test jmp dec_begin dma_test: sub edx, ecx ; rva remain cycles cmp edx, dwot[dma_c] ; cmp rva - dma_c ja dma_burn_out sub dwot[dma_c], edx mov edx, dwot[esp+16] mov dwot[curCnt], edx jmp _ret dma_burn_out: mov dwot[dma_c], 0 mov eax, dwot[dma_c] add dwot[curCnt], eax dec_begin: cmp wot[__pc], 0ffffh jne _noHit int 3 _noHit: movzx eax, wot[__pc] movzx esi, ax and eax, 1FFFh shr esi, 13 mov edx, dwot[cpuBanks+esi*4] lea ebx, [edx+eax] ; save pc ... inc wot[__pc] movzx esi, byt[ebx] ; load now PC ... mov dwot[curOus], esi jmp dwot[OPTAB+esi*4] getmem_ptr: mov eax, dwot[esp+4] cmp ax, 07FFh ja prg_l and eax, 07FFh lea eax, [ram+eax] ret prg_l: movzx ecx, ax and eax, 1FFFh shr ecx, 13 mov ecx, dwot[cpuBanks+ecx*4] lea eax, [eax+ecx] ret include opr.asm include mmu.asm include $$$none.asm ; AND OP29: ; #$ call __imm_r call __and jmp peek_int OP25: ; zero page call __zrp_r call __and jmp peek_int OP35: ; zero page x call __zrpx_r call __and jmp peek_int OP2D: ; abs call __abs_r call __and jmp peek_int OP3D: ; abs x call __absx_r call __and call __chk_cross_page jmp peek_int OP39: ; abs y call __absy_r call __and call __chk_cross_page jmp peek_int OP21: ; x indirect call __xid_r call __and jmp peek_int OP31: ; indirect y call __idy_r call __and call __chk_cross_page jmp peek_int ; ORA OP09: ; #$ call __imm_r call __ora jmp peek_int OP05: ; zero page call __zrp_r call __ora jmp peek_int OP15: ; zero page x call __zrpx_r call __ora jmp peek_int OP0D: ; abs call __abs_r call __ora jmp peek_int OP1D: ; abs x call __absx_r call __ora call __chk_cross_page jmp peek_int OP19: ; abs y call __absy_r call __ora call __chk_cross_page jmp peek_int OP01: ; x indirect call __xid_r call __ora jmp peek_int OP11: ; indirect y call __idy_r call __ora call __chk_cross_page jmp peek_int ; EOR OP49: ; #$ call __imm_r call __eor jmp peek_int OP45: ; zero page call __zrp_r call __eor jmp peek_int OP55: ; zero page x call __zrpx_r call __eor jmp peek_int OP4D: ; abs call __abs_r call __eor jmp peek_int OP5D: ; abs x call __absx_r call __eor call __chk_cross_page jmp peek_int OP59: ; abs y call __absy_r call __eor call __chk_cross_page jmp peek_int OP41: ; x indirect call __xid_r call __eor jmp peek_int OP51: ; indirect y call __idy_r call __eor call __chk_cross_page jmp peek_int ; ADC OP69: ; #$ call __imm_r call __adc jmp peek_int OP65: ; zero page call __zrp_r call __adc jmp peek_int OP75: ; zero page x call __zrpx_r call __adc jmp peek_int OP6D: ; abs call __abs_r call __adc jmp peek_int OP7D: ; abs x call __absx_r call __adc call __chk_cross_page jmp peek_int OP79: ; abs y call __absy_r call __adc call __chk_cross_page jmp peek_int OP61: ; x indirect call __xid_r call __adc jmp peek_int OP71: ; indirect y call __idy_r call __adc jmp peek_int ; SBC ;OPEB: OPE9: ; #$ call __imm_r call __sbc jmp peek_int OPE5: ; zero page call __zrp_r call __sbc jmp peek_int OPF5: ; zero page x call __zrpx_r call __sbc jmp peek_int OPED: ; abs call __abs_r call __sbc jmp peek_int OPFD: ; abs x call __absx_r call __sbc call __chk_cross_page jmp peek_int OPF9: ; abs y call __absy_r call __sbc call __chk_cross_page jmp peek_int OPE1: ; x indirect call __xid_r call __sbc jmp peek_int OPF1: ; indirect y call __idy_r call __sbc jmp peek_int ; DEC OPC6: ; zero page call __zrp_r call __dec call __zrp_w jmp peek_int OPD6: ; zero page x call __zrpx_r call __dec call __zrpx_w jmp peek_int OPCE: ; abs call __abs_r call __dec call __abs_w jmp peek_int OPDE: ; abs x call __absx_r call __dec call __absx_w jmp peek_int OPCA: ; dex call __dex jmp peek_int OP88: ; dey call __dey jmp peek_int ; INC OPE6: ; zero page call __zrp_r call __inc call __zrp_w jmp peek_int OPF6: ; zero page x call __zrpx_r call __inc call __zrpx_w jmp peek_int OPEE: ; abs call __abs_r call __inc call __abs_w jmp peek_int OPFE: ; abs x call __absx_r call __inc call __absx_w jmp peek_int OPE8: ; inx call __inx jmp peek_int OPC8: ; iny call __iny jmp peek_int ; BIT OP24: ; zero page call __zrp_r call __bit jmp peek_int OP2C: ; abs call __abs_r call __bit jmp peek_int ; ASL OP0A: ; ASL_A call __asl_a jmp peek_int OP06: ; zero page call __zrp_r call __asl call __zrp_w jmp peek_int OP16: ; zero page call __zrpx_r call __asl call __zrpx_w jmp peek_int OP0E: ; abs call __abs_r call __asl call __abs_w jmp peek_int OP1E: ; abs x call __abs_r call __asl call __abs_w jmp peek_int ; LSR OP4A: ; LSR_A call __lsr_a jmp peek_int OP46: ; zero page call __zrp_r call __lsr call __zrp_w jmp peek_int OP56: ; zero page call __zrpx_r call __lsr call __zrpx_w jmp peek_int OP4E: ; abs call __abs_r call __lsr call __abs_w jmp peek_int OP5E: ; abs x call __abs_r call __lsr call __abs_w jmp peek_int ; ROL OP2A: ; rol a call __rol_a jmp peek_int OP26: ; zero page call __zrp_r call __rol call __zrp_w jmp peek_int OP36: ; zero page x call __zrpx_r call __rol call __zrpx_w jmp peek_int OP2E: ; abs call __abs_r call __rol call __abs_w jmp peek_int OP3E: ; abs x call __absx_r call __rol call __absx_w jmp peek_int ; ROR OP6A: ; ror a call __ror_a jmp peek_int OP66: ; zero page call __zrp_r call __ror call __zrp_w jmp peek_int OP76: ; zero page x call __zrpx_r call __ror call __zrpx_w jmp peek_int OP6E: ; abs call __abs_r call __ror call __abs_w jmp peek_int OP7E: ; abs x call __absx_r call __ror call __absx_w jmp peek_int ; LDA OPA9: ; #$ call __imm_r call __lda jmp peek_int OPA5: ; zero page call __zrp_r call __lda jmp peek_int OPB5: ; zero page x call __zrpx_r call __lda jmp peek_int OPAD: ; abs call __abs_r call __lda jmp peek_int OPBD: ; abs x call __absx_r call __lda call __chk_cross_page jmp peek_int OPB9: ; abs y call __absy_r call __lda call __chk_cross_page jmp peek_int OPA1: ; x indirect call __xid_r call __lda jmp peek_int OPB1: ; indirect y call __idy_r call __lda call __chk_cross_page jmp peek_int ; X OPA2: ; #$ call __imm_r call __ldx jmp peek_int OPA6: ; zero page call __zrp_r call __ldx jmp peek_int OPB6: ; zero page y call __zrpy_r call __ldx jmp peek_int OPAE: ; abs call __abs_r call __ldx jmp peek_int OPBE: ; abs y call __absy_r call __ldx call __chk_cross_page jmp peek_int ; Y OPA0: ; #$ call __imm_r call __ldy jmp peek_int OPA4: ; zero page call __zrp_r call __ldy jmp peek_int OPB4: ; zero page x call __zrpx_r call __ldy jmp peek_int OPAC: ; abs call __abs_r call __ldy jmp peek_int OPBC: ; abs x call __absx_r call __ldy call __chk_cross_page jmp peek_int ; STA OP85: ; zero page call __zrp_get call __sta call __zrp_w jmp peek_int OP95: ; zero page x call __zrpx_get call __sta call __zrpx_w jmp peek_int OP8D: ; abs call __abs_get call __sta call __abs_w jmp peek_int OP9D: ; abs x call __absx_get call __sta call __absx_w jmp peek_int OP99: ; abs y call __absy_get call __sta call __absy_w jmp peek_int OP81: ; x indirect call __xid_get call __sta call __xid_w jmp peek_int OP91: ; indirect y call __idy_get call __sta call __idy_w jmp peek_int ; X OP86: ; zero page call __zrp_get call __stx call __zrp_w jmp peek_int OP96: ; zero pgae y call __zrpy_get call __stx call __zrpy_w jmp peek_int OP8E: ; abs call __abs_get call __stx call __abs_w jmp peek_int ; Y OP84: ; zero page call __zrp_get call __sty call __zrp_w jmp peek_int OP94: ; zero pgae x call __zrpx_get call __sty call __zrpx_w jmp peek_int OP8C: ; abs call __abs_get call __sty call __abs_w jmp peek_int ; CMP OPC9: ; #$ call __imm_r call __cmp jmp peek_int OPC5: ; zero page call __zrp_r call __cmp jmp peek_int OPD5: ; zero page x call __zrpx_r call __cmp jmp peek_int OPCD: ; abs call __abs_r call __cmp jmp peek_int OPDD: ; abs x call __absx_r call __cmp call __chk_cross_page jmp peek_int OPD9: ; abs y call __absy_r call __cmp call __chk_cross_page jmp peek_int OPC1: ; x indirect call __xid_r call __cmp jmp peek_int OPD1: ; indirect y call __idy_r call __cmp call __chk_cross_page jmp peek_int ; X OPE0: ; #$ call __imm_r call __cpx jmp peek_int OPE4: ; zero page call __zrp_r call __cpx jmp peek_int OPEC: ; abs call __abs_r call __cpx jmp peek_int ; Y OPC0: ; #$ call __imm_r call __cpy jmp peek_int OPC4: ; zero page call __zrp_r call __cpy jmp peek_int OPCC: ; abs call __abs_r call __cpy jmp peek_int align 16 peek_int: movzx ecx, byt[curOus] movd xmm5, ecx movzx eax, wot[__pc] movd xmm6, eax mov edx, dwot[optab+ecx*4] add dwot[curCnt], edx mov eax, dwot[int_pending] jmp [eax*4+INTAB] __no: jmp main_loop __irq: and dwot[int_pending], 2 ; clr pending flag ... call _DoIRQ ; do IRQ jmp main_loop __nmi: __both: and dwot[int_pending], 1 call _DoNMI ; do NMI jmp main_loop INTAB dd __no, __irq, __nmi, __both exec2a03 endp end
最终版本
FastCall2A03.asm
.686 ; create 32 bit code
.mmx
.xmm
.model flat, stdcall ; 32 bit memory model
option casemap :none ; case sensitive
; ===========================================================================
;
;
;
; 2A03 Instruction comment from nesdev.com (nesdev_weekly\www\6502.txt)
;
;
;
; ===========================================================================
;=======================
; Interrupt
;=======================
NMI_VECTOR equ FFFAh ; nmi
RES_VECTOR equ FFFCh ; reset
IRQ_VECTOR equ FFFEh ; irq
NMI_FLAG equ 2 ; nmi interrupt pending flag
IRQ_FLAG equ 1 ; irq interrupt pending flag
;=======================
; Pro Status
;=======================
C_FLAG equ 01h ; 1: carry?
Z_FLAG equ 02h ; 1: zero
I_FLAG equ 04h ; 1: intterrupt enable
D_FLAG equ 08h ; 1: dec mode nes did not use this mode
B_FLAG equ 10h ; 1: software intterrupt flag
R_FLAG equ 20h ; 1: this flag is reserved
V_FLAG equ 40h ; 1: overflow flag
N_FLAG equ 80h ; 1: negative flag
INT_C equ 7
DEBUG2A03 equ 0
byt equ byte ptr
wot equ word ptr
dwot equ dword ptr
$a equ dword ptr[ebx] ; 0
$x equ dword ptr[ebx+4] ; 1
$y equ dword ptr[ebx+8] ; 2
$s equ dword ptr[ebx+12] ; 3
$p equ dword ptr[ebx+16] ; 4
$pc equ dword ptr[ebx+20] ; 5
$ct equ dword ptr[ebx+24] ; 6
$t1 equ dword ptr[ebx+28] ; 7
$t2 equ dword ptr[ebx+32] ; 8
$t3 equ dword ptr[ebx+36] ; 9
ALIGNXMM equ align 16
;=======================
; extern symbols
;=======================
extrn GetCPUPtr@4:proc
extrn CpuAMread@4:proc
extrn CpuAMwrite@8:proc
extrn CpuAMreadW@4:proc
extrn CopyREGForDebug@4:proc
extrn SaveStackFrame@0:proc
extrn CheckStackFrame@0:proc
extrn ram:far
extrn regs:far
extrn zn_t:far
extrn dma_c:far
extrn cpuBanks:far
extrn int_pending:far
;===================
; Function
;===================
.code
FastCall2A03 proc C
option prologue:none, epilogue:none
push ebx ; - U save old frame
push esi ; - V save old frame
push edi ; - U save old frame
lea ebx, regs ; - V save old frame
mov eax, dwot[esp+16] ; - U load dispatch cycles->arg1
mov $ct, 0 ; - V/N reset counter
ALIGNXMM
main_loop:
mov eax, dwot[esp+16] ; - U dis c
mov edx, $ct ; - V load cycles
mov ecx, dwot[dma_c]; -V/N
cmp eax, edx ; - U dis c/ct
nop
jg to_dma_test
mov eax, $ct
trap_exit:
pop edi
pop esi
pop ebx
ret ; proc ret ...
ALIGNXMM
to_dma_test:
cmp ecx, 0
jle dec_begin
xor edi, edi
sub eax, edx ; rva cycles
cmp ecx, eax
jge remain_out
add $ct, ecx ; dma buring out
mov dwot[dma_c], edi
jmp dec_begin
ALIGNXMM
remain_out:
sub ecx, eax ; remain cycles buring out
mov eax, dwot[esp+16]
mov dwot[dma_c], ecx
jmp trap_exit
ALIGNXMM
dec_begin:
mov ecx, $pc
nop
mov edi, ecx
lea edx, [ecx+1]
mov $pc, edx
and ecx, 0FFFFh
shr ecx, 13
and edi, 01FFFh
mov esi, dwot[cpuBanks+ecx*4]
nop
movzx eax, byt[esi+edi] ;- N
add edi, esi
jmp [OPTAB+eax*4]
; instr decode begin ...
include ARITH.asm
include ATOM.asm
include CMP.asm
include JCC.asm
include LOGIC.asm
include PROC.asm
include PSW.asm
include READ.asm
include REMAIN.asm
include RTOR.asm
include SHIFT.asm
include SOFT-INT.asm
include STACK.asm
include TEST.asm
include WRITE.asm
ALIGNXMM
PollInt:
mov eax, dwot[int_pending]
and eax, 3
jmp dwot[INT_TAB+eax*4]
ALIGNXMM
IRQ_PROC:
and eax, 2 ; clr IRQ flag ...
mov ecx, $s
mov dwot[int_pending], eax
xor edx, edx
mov eax, $p
mov edx, $pc
mov wot[ecx+ram+0100h-1], dx
and ax, 0EFh ; clr B flag ...
mov byt[ecx+ram+0100h-2], al
sub cl, 3
or eax, I_FLAG
mov edx, $ct
mov $s, ecx
mov $p, eax
add edx, INT_C
mov eax, dwot[cpuBanks+28]
mov cx, wot[eax+01FFEh] ; set IRQ addr
nop
mov $ct, edx
mov $pc, ecx
jmp main_loop
ALIGNXMM
NMI_PROC:
and eax, 1 ; clr NMI flag ...
mov ecx, $s
mov dwot[int_pending], eax
xor edx, edx
mov eax, $p
mov edx, $pc
mov wot[ecx+ram+0100h-1], dx
and ax, 0EFh ; clr B flag ...
mov byt[ecx+ram+0100h-2], al
sub cl, 3
or eax, I_FLAG
mov edx, $ct
mov $s, ecx
mov $p, eax
add edx, INT_C
mov eax, dwot[cpuBanks+28]
mov cx, wot[eax+01FFAh] ; set NMI addr
nop
mov $ct, edx
mov $pc, ecx
jmp main_loop
ALIGNXMM
NO_DEAL:
jmp main_loop
INT_TAB dd NO_DEAL, IRQ_PROC, NMI_PROC, NMI_PROC
FastCall2A03 endp
setNMI proc C
option prologue:none, epilogue:none
or dwot[int_pending], NMI_FLAG
ret
setNMI endp
setIRQ proc C
option prologue:none, epilogue:none
or dwot[int_pending], IRQ_FLAG
ret
setIRQ endp
fastNMI proc C
option prologue:none, epilogue:none
fastNMI endp
fastIRQ proc C
option prologue:none, epilogue:none
fastIRQ endp
cpuReset proc C
option prologue:none, epilogue:none
push ebx
lea ebx, regs
xor ecx, ecx
or $p, 022h
mov $a, ecx
mov $x, ecx
mov $y, ecx
mov $s, 0FFh
mov eax, dwot[cpuBanks+28]
mov ecx, dwot[eax+01FFCh] ; set RESET addr
mov $pc, ecx
pop ebx
ret
cpuReset endp
end
ARITH.asm
;***
; ADC
; 69: #$ 2 cycles
; 65: ZERO PAGE 3 cycles
; 75: ZERO PAGE X 4 cycles
; 6D: ABS 4 cycles
; 7D: ABS X 4 cycles (crossing page ++ cycles)
; 79: ABS Y 4 cycles (crossing page ++ cycles)
; 61: X INDIRECT 6 cycles
; 71: INDIRECT Y 4 cycles (crossing page ++ cycles)
; Algorithm:
;
; unsigned int temp = src + AC + (IF_CARRY() ? 1 : 0);
; SET_ZERO(temp & 0xff); /* This is not valid in decimal mode */
; if (IF_DECIMAL()) {
; if (((AC & 0xf) + (src & 0xf) + (IF_CARRY() ? 1 : 0)) > 9) {
; temp += 6;
; }
; SET_SIGN(temp);
; SET_OVERFLOW(!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
; if (temp > 0x99) {
; temp += 96;
; }
; SET_CARRY(temp > 0x99);
; } else {
; SET_SIGN(temp);
; SET_OVERFLOW(!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
; SET_CARRY(temp > 0xff);
; }
; AC = ((BYTE) temp);
;*************************************************
OP69: ; ADC #$ 2 cycles
mov al, byt[edi+1] ; - U eax <- val
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 2 ; - V 2 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OP65: ; ADC ZERO PAGE 3 cycles
movzx eax, byt[edi+1] ; - N load zero page inx
movzx eax, byt[ram+eax] ; - N load val
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 3 ; - V 3 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OP75: ; ADC ZERO PAGE X 4 cycles
mov al, byt[edi+1] ; - U load zero page inx
nop ; - V spare
add eax, $x ; - U limit byte
nop ; - V spare
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov al, byt[ram+eax] ; - U
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OP6D: ; ADC ABS 4 cycles
mov ax, wot[edi+1] ; - U load abs index
nop ; - V spare
push eax ; - U push stack to to call mem read (__stdcall call)
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 2 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OP7D: ; ADC ABS X 4 cycles (corssing page)
mov ax, wot[edi+1] ; - U load abs index
mov cx, wot[ebx+4] ; - V load x
and ecx, 11111111b ; - U limit byte
nop ; - V spare
add ecx, eax ; - U goal inx
nop ; - V spare
push ecx ; - U
nop ; - V spare
cmp ah, ch ; - U cmp test C
nop ; - V spare
adc $ct, 0
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 2 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OP79: ; ADC ABS Y 4 cycles (corssing page)
mov ax, wot[edi+1] ; - U load abs index
mov cx, wot[ebx+8] ; - V load y
and ecx, 11111111b ; - U limit byte
nop ; - V spare
add ecx, eax ; - U goal inx
nop ; - V spare
push ecx ; - U
nop ; - V spare
cmp ah, ch ; - U cmp test C
nop ; - V spare
adc $ct, 0
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 2 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OP61: ; ADC X INDIRECT 6 cycles
movzx eax, byt[edi+1] ; - N load val and clr bit
add al, byt[ebx+4] ; - U zero page with x
nop ; - V
movzx ecx, wot[ram+eax] ; - N
push ecx
nop
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 6 ; - V 6 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OP71: ; ADC INDIRECT Y
movzx eax, byt[edi+1] ; - N load zero inx
mov ax, wot[eax+ram] ; - U load zero page inx's val
mov cx, wot[ebx+8] ; - load y
and ecx, 11111111b ; - U limit byte
nop ; - V spare
add ecx, eax ; with y
nop ; - V spare
push ecx ; push stack
nop ; - V spare
cmp ah ,ch ; test cross page ?
nop ; - V spare
adc $ct, 0
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
shr edx, 1 ; - U with C
nop ; - V spare
adc cl, al ; - U ADC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
;***
; SBC
; EB: #$ 2 cycles (unofficial)
; E9: #$ 2 cycles
; E5: ZERO PAGE 3 cycles
; F5: ZERO PAGE X 4 cycles
; ED: ABS 4 cycles
; FD: ABS X 4 cycles (crossing page ++ cycles)
; F9: ABS Y 4 cycles (crossing page ++ cycles)
; E1: X INDIRECT 6 cycles
; F1: INDIRECT Y 4 cycles (crossing page ++ cycles)
; Algorithm:
;
; unsigned int temp = AC - src - (IF_CARRY() ? 0 : 1);
; SET_SIGN(temp);
; SET_ZERO(temp & 0xff); /* Sign and Zero are invalid in decimal mode */
; SET_OVERFLOW(((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
; if (IF_DECIMAL()) {
; if ( ((AC & 0xf) - (IF_CARRY() ? 0 : 1)) < (src & 0xf)) /* EP */ {
; temp -= 6;
; }
; if (temp > 0x99) {
; temp -= 0x60;
; }
; }
; SET_CARRY(temp < 0x100);
; AC = (temp & 0xff);
;*************************************************
OPE9: ; SBC #$ 2 cycles
mov al, byt[edi+1] ; - U eax <- val
nop ; - V spare
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 2 ; - V 2 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OPE5: ; SBC ZERO PAGE 3 cycles
movzx eax, byt[edi+1] ; - N load zero page inx
movzx eax, byt[ram+eax] ; - N load val
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 3 ; - V 3 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OPF5: ; SBC ZERO PAGE X 4 cycles
mov al, byt[edi+1] ; - U load zero page inx
nop ; - V spare
add eax, $x ; - U limit byte
nop ; - V spare
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov al, byt[ram+eax] ; - U
nop ; - V spare
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OPED: ; SBC ABS 4 cycles
mov ax, wot[edi+1] ; - U load abs index
nop ; - V spare
push eax ; - U push stack to to call mem read (__stdcall call)
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 2 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OPFD: ; SBC ABS X 4 cycles (corssing page)
mov ax, wot[edi+1] ; - U load abs index
mov cx, wot[ebx+4] ; - V load x
and ecx, 11111111b ; - U limit byte
nop ; - V spare
add ecx, eax ; - U goal inx
nop ; - V spare
push ecx ; - U
nop ; - V spare
cmp ah, ch ; - U cmp test C
nop ; - V spare
adc $ct, 0
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 2 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OPF9: ; SBC ABS Y 4 cycles (corssing page)
mov ax, wot[edi+1] ; - U load abs index
mov cx, wot[ebx+8] ; - V load y
and ecx, 11111111b ; - U limit byte
nop ; - V spare
add ecx, eax ; - U goal inx
nop ; - V spare
push ecx ; - U
nop ; - V spare
cmp ah, ch ; - U cmp test C
nop ; - V spare
adc $ct, 0
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 2 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OPE1: ; SBC X INDIRECT
movzx eax, byt[edi+1] ; - N load val and clr bit
add al, byt[ebx+4] ; - U zero page with x
nop ; - V
movzx ecx, wot[ram+eax] ; - N
push ecx
nop
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 6 ; - V 6 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
OPF1: ; SBC INDIRECT Y
movzx eax, byt[edi+1] ; - N load zero inx
mov ax, wot[eax+ram] ; - U load zero page inx's val
mov cx, wot[ebx+8] ; - load y
and ecx, 11111111b ; - U limit byte
nop ; - V spare
add ecx, eax ; with y
nop ; - V spare
push ecx ; push stack
nop ; - V spare
cmp ah ,ch ; test cross page ?
nop ; - V spare
adc $ct, 0
nop ; - V spare
call CpuAMread@4
and eax, 255 ; - U limit byte
nop ; - V spare
; SBC - MAIN
mov edx, $p ; - U load flag
mov ecx, $a ; - V load acc
and edx, 00111101b ; - U clr N-V-Z flag
and ecx, 11111111b ; - V limit byte
xor edx, 1 ; - U neg C flag ...
nop ; - V spare
shr edx, 1 ; - U with C
nop ; - V spare
sbb cl, al ; - U SBC opr (eax free)
nop ; - V spare
seto al ; - N SETcc set O flag
rcl edx, 1 ; - U save C flag ...
mov esi, $pc ; - V load PC
xor edx, 1 ; - NEG C
nop ; - V spare
shl eax, 6 ; - U fit pos with O flag
add esi, 1 ; - V opcode num ++
or edx, eax ; - U reset O flag (eax free)
mov eax, $ct ; - V load cycles cnt
or edx, dwot[zn_t+ecx*4] ; - U reset Z-N flag
add eax, 4 ; - V 4 cycles
mov $ct, eax ; - U write back cycle cnt (eax)
mov $a, ecx ; - V write back acc (ecx)
mov $pc, esi ; - U write PC (esi)
mov $p, edx ; - V write flag (edx)
jmp PollInt ; deal over begin poll intterupt
ATOM.asm
;***
; DEC
; C6: ZERO PAGE 5 cycles
; D6: ZERO PAGE X 6 cycles
; CE: ABS 6 cycles
; DE: ABS X 7 cycles
; X CA: REG 2 cycles
; Y 88: REG 2 cycles
; Algorithm:
;
; src = (src - 1) & 0xff;
; SET_SIGN(src);
; SET_ZERO(src);
; STORE(address, (src));
;*************************************************
OPC6: ; DEC ZERO PAGE 5 Cycles
movzx esi, byt[edi+1] ; - N load zero page addr
movzx eax, byt[ram+esi] ; - N load addr's val
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
sub al, 1 ; - V DEC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 1 ; - V opcode nums
mov byt[ram+esi], al ; - U write back mem (eax free)
nop ; - V spare
mov eax, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add eax, 5 ; - U 5 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, eax ; - V write back cycles cnt (eax)
jmp PollInt
OPD6: ; DEC ZERO PAGE X 6 cycles
movzx esi, byt[edi+1] ; - N load zero page addr
add esi, $x ; - U with x
nop ; - V spare
and esi, 11111111b ; - U limit byte
nop ; - V spare
movzx eax, byt[ram+esi] ; - N load addr's val
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
sub al, 1 ; - V DEC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 1 ; - V opcode nums
mov byt[ram+esi], al ; - U write back mem (eax free)
nop ; - V spare
mov eax, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add eax, 6 ; - U 6 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, eax ; - V write back cycles cnt (eax)
jmp PollInt
OPCE: ; DEC ABS 6 cycles
movzx eax, wot[edi+1] ; - N get abs addr
push eax ; - U push stack
mov esi, eax ; - V save old frame
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
sub al, 1 ; - V DEC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 2 ; - V opcode nums
mov edi, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add edi, 6 ; - U 6 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, edi ; - V write back cycles cnt (eax)
push eax
push esi
call CpuAMwrite@8
jmp PollInt
OPDE: ; DEC ABS X 7 cycles
movzx eax, wot[edi+1] ; - N get abs addr
movzx ecx, byt[ebx+4]
add ax, cx
nop
push eax ; - U push stack
mov esi, eax ; - V save old frame
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
sub al, 1 ; - V DEC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 2 ; - V opcode nums
mov edi, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add edi, 6 ; - U 6 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, edi ; - V write back cycles cnt (eax)
push eax
push esi
call CpuAMwrite@8
jmp PollInt
OPCA: ; DEX 2 cycles
mov eax, $x ; - U load x
mov edx, $p ; - V load flag
and dl, 07Dh ; - U clr N-Z flag
sub al, 1 ; - V DEX opr
or dl, byt[zn_t+eax*4] ; - U reset Z-N flag
mov byt[ebx+4], al ; - V write back mem (eax free)
mov eax, $ct ; - U load cycles cnt
mov $p, edx ; - V write back flag (edx)
add eax, 2 ; - U 2 cycles
nop ; - V spare
mov $ct, eax ; - V write back cycles cnt (eax)
nop ; - V spare
jmp PollInt
OP88: ; DEY
mov eax, $y ; - U load y
mov edx, $p ; - V load flag
and dl, 07Dh ; - U clr N-Z flag
sub al, 1 ; - V DEY opr
or dl, byt[zn_t+eax*4] ; - U reset Z-N flag
mov byt[ebx+8], al ; - V write back mem (eax free)
mov eax, $ct ; - U load cycles cnt
mov $p, edx ; - V write back flag (edx)
add eax, 2 ; - U 2 cycles
nop ; - V spare
mov $ct, eax ; - V write back cycles cnt (eax)
nop ; - V spare
jmp PollInt
;***
; INC
; E6: ZERO PAGE 5 cycles
; F6: ZERO PAGE X 6 cycles
; EE: ABS 6 cycles
; FE: ABS X 7 cycles
; X E8: REG 2 cycles
; Y C8: REG 2 cycles
; Algorithm:
;
; src = (src + 1) & 0xff;
; SET_SIGN(src);
; SET_ZERO(src);
; STORE(address, (src));
;*************************************************
OPE6: ; INC ZERO PAGE 5 cycles
movzx esi, byt[edi+1] ; - N load zero page addr
movzx eax, byt[ram+esi] ; - N load addr's val
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
add al, 1 ; - V INC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 1 ; - V opcode nums
mov byt[ram+esi], al ; - U write back mem (eax free)
nop ; - V spare
mov eax, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add eax, 5 ; - U 5 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, eax ; - V write back cycles cnt (eax)
jmp PollInt
OPF6: ; INC ZERO PAGE X 6 cycles
movzx esi, byt[edi+1] ; - N load zero page addr
add esi, $x ; - U with x
nop ; - V spare
and esi, 11111111b ; - U limit byte
nop ; - V spare
movzx eax, byt[ram+esi] ; - N load addr's val
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
add al, 1 ; - V INC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 1 ; - V opcode nums
mov byt[ram+esi], al ; - U write back mem (eax free)
nop ; - V spare
mov eax, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add eax, 6 ; - U 6 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, eax ; - V write back cycles cnt (eax)
jmp PollInt
OPEE: ; INC ABS 6 cycles
movzx eax, wot[edi+1] ; - N get abs addr
push eax ; - U push stack
mov esi, eax ; - V save old frame
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
add al, 1 ; - V INC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 2 ; - V opcode nums
mov edi, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add edi, 6 ; - U 6 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, edi ; - V write back cycles cnt (eax)
push eax
push esi
call CpuAMwrite@8
jmp PollInt
OPFE: ; INC ABS X 7 cycles
movzx eax, wot[edi+1] ; - N get abs addr
movzx ecx, byt[ebx+4]
add ax, cx
nop
push eax ; - U push stack
mov esi, eax ; - V save old frame
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov edx, $p ; - U load flag
mov ecx, $pc ; - V load PC
and dl, 07Dh ; - U clr N-Z flag
add al, 1 ; - V INC opr
or edx, dwot[zn_t+eax*4] ; - U reset Z-N flag
add ecx, 2 ; - V opcode nums
mov edi, $ct ; - U load cycles cnt
mov $pc, ecx ; - V write back PC (ecx)
add edi, 7 ; - U 7 cycles
nop ; - V spare
mov $p, edx ; - U write back flag (edx)
mov $ct, edi ; - V write back cycles cnt (eax)
push eax
push esi
call CpuAMwrite@8
jmp PollInt
OPE8: ; INX
mov eax, $x ; - U load x
mov edx, $p ; - V load flag
and dl, 07Dh ; - U clr N-Z flag
add al, 1 ; - V INX opr
or dl, byt[zn_t+eax*4] ; - U reset Z-N flag
mov byt[ebx+4], al ; - V write back mem (eax free)
mov eax, $ct ; - U load cycles cnt
mov $p, edx ; - V write back flag (edx)
add eax, 2 ; - U 2 cycles
nop ; - V spare
mov $ct, eax ; - V write back cycles cnt (eax)
nop ; - V spare
jmp PollInt
OPC8: ; INY
mov eax, $y ; - U load x
mov edx, $p ; - V load flag
and dl, 07Dh ; - U clr N-Z flag
add al, 1 ; - V INY opr
or dl, byt[zn_t+eax*4] ; - U reset Z-N flag
mov byt[ebx+8], al ; - V write back mem (eax free)
mov eax, $ct ; - U load cycles cnt
mov $p, edx ; - V write back flag (edx)
add eax, 2 ; - U 2 cycles
nop ; - V spare
mov $ct, eax ; - V write back cycles cnt (eax)
nop ; - V spare
jmp PollInt
CMP.asm
;***
; CMP
; C9: #$ 2 cycles
; C5: ZERO PAGE 3 cycles
; D5: ZERO PAGE X 4 cycles
; CD: ABS 4 cycles
; DD: ABS X 4 cycles (crossing page ++ cycles)
; D9: ABS Y 4 cycles (crossing page ++ cycles)
; C1: X INDIRECT 6 cycles
; D1: INDIRECT Y 5 cycles (crossing page ++ cycles)
; X E0: #$ 2 cycles
; X E4: ZERO PAGE 3 cycles
; X EC: ABS 4 cycles
; Y C0: #$ 2 cycles
; Y C4: ZERO PAGE 3 cycles
; Y CC: ABS 4 cycles
;
; Algorithm:
;
; src = AC - src;
; SET_CARRY(src < 0x100);
; SET_SIGN(src);
; SET_ZERO(src &= 0xff);
;*************************************************
OPC9: ; CMP #$ 2 cycles
movzx eax, byt[edi+1] ; - N load val
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 2 ; - U 2 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPC5: ; CMP ZERO PAGE 3 cycles
movzx eax, byt[edi+1] ; - N load addr
movzx eax, byt[eax+ram] ; - N load val
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 3 ; - U 3 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPD5: ; CMP ZERO PAGE X 4 cycles
movzx eax, byt[edi+1] ; - N load addr
add al, byt[ebx+4] ; - U with x
nop ; - V spare
movzx eax, byt[eax+ram] ; - N load val
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 4 ; - U 4 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPCD: ; CMP ABS 4 cycles
movzx eax, wot[edi+1] ; - N load abs addr
push eax ; - U
nop ; - V spare
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 4 ; - U 4 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 2 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPDD: ; CMP ABS X (test cross page)
movzx eax, wot[edi+1] ; - N load abs addr
movzx ecx, byt[ebx+4] ; - N load x
add ecx, eax ; - U with x
nop ; - V spare
push ecx ; - U
nop ; - V spare
cmp ah, ch ; - U
nop ; - V spare
add $ct, 0 ; - U
nop ; - V spare
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 4 ; - U 4 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 2 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPD9: ; CMP ABS Y (test cross page)
movzx eax, wot[edi+1] ; - N load abs addr
movzx ecx, byt[ebx+8] ; - N load y
add ecx, eax ; - U with y
nop ; - V spare
push ecx ; - U
nop ; - V spare
cmp ah, ch ; - U
nop ; - V spare
add $ct, 0 ; - U
nop ; - V spare
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 4 ; - U 4 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 2 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPC1: ; CMP X INDIRECT 6 cycles
movzx eax, byt[edi+1] ; - N load addr
add al, byt[ebx+4] ; - U with x
nop ; - V spare
mov cx, wot[eax+ram] ; - U load addr
nop ; - V spare
push ecx
nop
call CpuAMread@4
and eax, 11111111b ; - U
nop ; - V spare
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 6 ; - U 6 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPD1: ; CMP INDIRECT Y (test cross page)
movzx eax, byt[edi+1] ; - N load abs addr
movzx eax, wot[ram+eax] ; - N ram liwst
movzx ecx, byt[ebx+8] ; - N load y
add ecx, eax ; - U with y
nop ; - V spare
push ecx ; - U
nop ; - V spare
cmp ah, ch ; - U
nop ; - V spare
add $ct, 0 ; - U
nop ; - V spare
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov ecx, $a ; - U load acc
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CMP opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 4 ; - U 4 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPE0: ; CPX #$
movzx eax, byt[edi+1] ; - N load val
mov ecx, $x ; - U load x
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CPX opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 2 ; - U 2 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPE4: ; CPX ZERO PAGE
movzx eax, byt[edi+1] ; - N load addr
movzx eax, byt[eax+ram] ; - N load val
mov ecx, $x ; - U load x
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CPX opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 3 ; - U 3 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPEC: ; CPX ABS
movzx eax, wot[edi+1] ; - N load abs addr
push eax ; - U
nop ; - V spare
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov ecx, $x ; - U load x
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CPX opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 4 ; - U 4 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 2 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPC0: ; CPY #$
movzx eax, byt[edi+1] ; - N load val
mov ecx, $y ; - U load y
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CPY opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 2 ; - U 2 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPC4: ; CPY ZERO PAGE
movzx eax, byt[edi+1] ; - N load addr
movzx eax, byt[eax+ram] ; - N load val
mov ecx, $y ; - U load y
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CPY opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 3 ; - U 3 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 1 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
OPCC: ; CPY ABS
movzx eax, wot[edi+1] ; - N load abs addr
push eax ; - U
nop ; - V spare
call CpuAMread@4
and eax, 11111111b ; - U limit byte
nop ; - V spare
mov ecx, $y ; - U load y
mov edx, $p ; - V load flag
and edx, 01111100b ; - U clr n-z-c flag
and ecx, 11111111b ; - V limit other bit
sub ecx, eax ; - U CPY opr
mov esi, $ct ; - V load cycles cnt
setnc al ; - N SETcc
or edx, eax ; - U reset C flag (eax free)
mov eax, $pc ; - V load PC
add esi, 4 ; - U 4 cycles
and ecx, 11111111b ; - V limit byte
or edx, dwot[ecx*4+zn_t] ; - U reset Z-N flag
add eax, 2 ; - V opcode num
mov $p, edx ; - U write back flag (edx)
mov $ct, esi ; - V write back cycles cnt (esi)
mov $pc, eax ; - U write back PC (eax)
nop ; - V spare
jmp PollInt
FastMMU.c
#include "..\NES\nestype.h"
extern NESB ram[0x800];
extern PNESB cpuBanks[8];
NESB NESSTDCALL CpuAMread (NESD ar32)
{
NESW ar = toNESW(ar32);
switch (ar >> 13)
{
case 0x00:
return ram[ar & 0x7FF];
case 0x01:
return ppuIOread(ar & 7);
case 0x02:
if (ar < 0x4100)
return apuIOread(ar32);
else
return 0;
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
return cpuBanks[ar >> 13][ar & 0x1FFF];
}
}
NESVOID NESSTDCALL CpuAMwrite (NESD ar32, NESD val32)
{
NESW ar = toNESW(ar32);
NESB val = toNESB(val32);
switch (ar >> 13)
{
case 0x00:
ram[ar & 0x7FF] = val;
return;
case 0x01:
ppuIOwrite(ar & 7, val);
return;
case 0x02:
if (ar < 0x4020)
{
apuIOwrite(ar, val);
return;
}
else
{
return;
}
case 0x03:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
cpuBanks[ar >> 13][ar & 0x1FFF] = val;
}
}
NESNAKED NESW NESSTDCALL CpuAMreadW (NESD addr)
{
__asm {
movzx eax, word ptr[esp+4]
cmp eax, 0x2000
jb __RAM_LOAD
mov ecx, eax
and eax, 0x1FFF
shr ecx, 13
mov edx, dword ptr[cpuBanks+ecx*4]
movzx eax, word ptr[edx+eax]
ret 4
align 16
__RAM_LOAD:
and eax, 0x7FF
movzx eax, word ptr[eax+ram]
ret 4
}
}
NESNAKED PNESD NESSTDCALL GetCPUPtr (NESD addr)
{
__asm {
movzx eax, word ptr[esp+4]
cmp eax, 0x2000
jb __RAM_LOAD
mov ecx, eax
and eax, 0x1FFF
shr ecx, 13
mov edx, dword ptr[cpuBanks+ecx*4]
lea eax, [edx+eax]
ret 4
align 16
__RAM_LOAD:
and eax, 0x7FF
lea eax, [eax+ram]
ret 4
}
}
global.c
__declspec(align(16)) int zn_t[256] =
{
0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80
}; // from virtuanes ...
__declspec(align(16)) int regs[20];
JCC.asm
; d7 - d0: N V R B D I Z C
OP90: ; BCC C Bit Clear JMP
test $p, 00000001b
je Fhit
jmp Fnhit
OPD0: ; BNE Z Bit Clear JMP
test $p, 00000010b
je Fhit
jmp Fnhit
OP10: ; BPL N Bit Clear JMP
test $p, 10000000b
je Fhit
jmp Fnhit
OP50: ; BVC V Bit Clear JMP
test $p, 01000000b
je Fhit
jmp Fnhit
OPB0: ; BCS C Bit Set JMP
test $p, 00000001b
jne Fhit
jmp Fnhit
OPF0: ; BEQ Z Bit Set JMP
test $p, 00000010b
jne Fhit
jmp Fnhit
OP30: ; BMI N Bit Set JMP
test $p, 10000000b
jne Fhit
jmp Fnhit
OP70: ; BVS V Bit Set JMP
test $p, 01000000b
jne Fhit
jmp Fnhit
ALIGNXMM
Fhit:
mov eax, $pc
mov edx, $ct
and eax, 0FFFFh
add edx, 3 ; hit 3 cycles
inc ax
movsx ecx, byt[edi+1]
add ax, cx
mov $pc, eax
mov $ct, edx
jmp PollInt
ALIGNXMM
Fnhit:
mov eax, $pc ; no hit 2 cycles
mov ecx, $ct
add ecx, 2
add eax, 1
mov $pc, eax
mov $ct, ecx
jmp PollInt
LOGIC.asm
;***
; ORA
; 09: #$ 2 cycles
; 05: ZERO PAGE 3 cycles
; 15: ZERO PAGE X 4 cycles
; 0D: ABS 4 cycles
; 1D: ABS X 4 cycles (crossing page ++ cycles)
; 19: ABS Y 4 cycles (crossing page ++ cycles)
; 01: X INDIRECT 6 cycles
; 11: INDIRECT Y 4 cycles (crossing page ++ cycles)
; Algorithm:
;
; src |= AC;
; SET_SIGN(src);
; SET_ZERO(src);
; AC = src;
;*************************************************
OP09: ; ORA #$
movzx eax, byt[edi+1] ; - N
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 2 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP05: ; ORA ZERO PAGE
movzx eax, byt[edi+1] ; - N
movzx eax, byt[ram+eax]
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 3 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP15: ; ORA ZERO PAGE X
movzx eax, byt[edi+1] ; - N
mov ecx, $x
and ecx, 255
add al, cl
movzx eax, byt[ram+eax]
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP0D: ; ORA ABS
movzx eax, wot[edi+1] ; - N
push eax
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP1D: ; ORA ABS X
movzx eax, wot[edi+1] ; - N
movzx ecx, byt[ebx+4] ; - N
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP19: ; ORA ABS Y
movzx eax, wot[edi+1] ; - N
movzx ecx, byt[ebx+8] ; - N
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP01: ; ORA X INDIRECT
movzx eax, byt[edi+1] ; - N
add al, byt[ebx+4]
nop
movzx eax, wot[ram+eax]
push eax
nop
call CpuAMread@4
and eax, 0FFh
nop
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 5 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP11: ; ORA INDIRECT Y
movzx eax, byt[edi+1] ; - N
movzx eax, wot[ram+eax]
movzx ecx, byt[ebx+8]
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
or al, dl ; - U ORA opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 5 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
;***
; EOR
; 49: #$ 2 cycles
; 45: ZERO PAGE 3 cycles
; 55: ZERO PAGE X 4 cycles
; 4D: ABS 4 cycles
; 5D: ABS X 4 cycles (crossing page ++ cycles)
; 59: ABS Y 4 cycles (crossing page ++ cycles)
; 41: X INDIRECT 6 cycles
; 51: INDIRECT Y 4 cycles (crossing page ++ cycles)
; Algorithm:
;
; src ^= AC;
; SET_SIGN(src);
; SET_ZERO(src);
; AC = src;
;*************************************************
OP49: ; EOR #$
movzx eax, byt[edi+1] ; - N
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 2 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP45: ; EOR ZERO PAGE
movzx eax, byt[edi+1] ; - N
movzx eax, byt[ram+eax]
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 3 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP55: ; EOR ZERO PAGE X
movzx eax, byt[edi+1] ; - N
mov ecx, $x
and ecx, 255
add al, cl
movzx eax, byt[ram+eax]
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP4D: ; EOR ABS
movzx eax, wot[edi+1] ; - N
push eax
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP5D: ; EOR ABS X
movzx eax, wot[edi+1] ; - N
movzx ecx, byt[ebx+4] ; - N
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP59: ; EOR ABS Y
movzx eax, wot[edi+1] ; - N
movzx ecx, byt[ebx+8] ; - N
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP41: ; EOR X INDIRECT
movzx eax, byt[edi+1] ; - N
add al, byt[ebx+4]
nop
movzx eax, wot[ram+eax]
push eax
nop
call CpuAMread@4
and eax, 0FFh
nop
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 5 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP51: ; EOR INDIRECT Y
movzx eax, byt[edi+1] ; - N
movzx eax, wot[ram+eax]
movzx ecx, byt[ebx+8]
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
xor al, dl ; - U EOR opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 5 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
;***
; AND
; 29: #$ 2 cycles
; 25: ZERO PAGE 3 cycles
; 35: ZERO PAGE X 4 cycles
; 2D: ABS 4 cycles
; 3D: ABS X 4 cycles (crossing page ++ cycles)
; 39: ABS Y 4 cycles (crossing page ++ cycles)
; 21: X INDIRECT 6 cycles
; 31: INDIRECT Y 4 cycles (crossing page ++ cycles)
; Algorithm:
;
; src &= AC;
; SET_SIGN(src);
; SET_ZERO(src);
; AC = src;
;*************************************************
OP29: ; AND #$
movzx eax, byt[edi+1] ; - N
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 2 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP25: ; AND ZERO PAGE
movzx eax, byt[edi+1] ; - N
movzx eax, byt[ram+eax]
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 3 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP35: ; AND ZERO PAGE X
movzx eax, byt[edi+1] ; - N
mov ecx, $x
and ecx, 255
add al, cl
movzx eax, byt[ram+eax]
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP2D: ; AND ABS
movzx eax, wot[edi+1] ; - N
push eax
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP3D: ; AND ABS X
movzx eax, wot[edi+1] ; - N
movzx ecx, byt[ebx+4] ; - N
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP39: ; AND ABS Y
movzx eax, wot[edi+1] ; - N
movzx ecx, byt[ebx+8] ; - N
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 2 ; - V opcode nums
add esi, 4 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP21: ; AND X INDIRECT
movzx eax, byt[edi+1] ; - N
add al, byt[ebx+4]
nop
movzx eax, wot[ram+eax]
push eax
nop
call CpuAMread@4
and eax, 0FFh
nop
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 5 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
OP31: ; AND INDIRECT Y
movzx eax, byt[edi+1] ; - N
movzx eax, wot[ram+eax]
movzx ecx, byt[ebx+8]
add ecx, eax
nop
push ecx
nop
cmp ah, ch
nop
adc $ct, 0
nop
call CpuAMread@4
and eax, 255
nop
mov ecx, $p
mov edx, $a
and al, dl ; - U AND opr
and cl, 07Dh
mov esi, $ct
mov edx, $pc
or ecx, dwot[zn_t+eax*4]
add edx, 1 ; - V opcode nums
add esi, 5 ; - U cycles
nop
mov $pc, edx
mov $a, eax
mov $ct, esi
mov $p, ecx
jmp PollInt ; begin deal int ...
PROC.asm
;***
; JMP
; 4C: ABS 3 cycles
; 6C: inDirect 5 cycles
; Algorithm:
;
; PC = (src);
;
;*************************************************
OP4C: ; JMP ABS
mov ax, wot[edi+1]
nop
mov ecx, $ct
mov $pc , eax
add ecx, 3
nop
mov $ct, ecx
nop
jmp PollInt
OP6C:
; in-direct JMP expection crossing page boundaries in 6C
; NES JMP(only 6C)'s BUG: if addr is 0x--FF(Crossing Page) IP's High Bit Will Not Add
;
; $2500: 33
; $25FF: 76
; $2600: 89
; $7574: 6C FF 25
; PC <- $7574
;
; Step1-> Get PC's Low Bit FF
; Step2-> Get PC's High Bit 25
; $(25FF-2600) will crossing page so low bit is $25FF high Bit is $2500
; jmp to $3376 ...
movzx eax, wot[edi+1] ; load indirect addr ...
push eax
add $ct, 5
cmp al, 0FFh ; low addr is FF ?
jne noCrossPage
mov $t1, eax
call CpuAMread@4
mov $t2, eax ; low bit
mov eax, $t1
sub eax, 0FFh
nop
push eax
nop
call CpuAMread@4
mov ecx, $t2 ; low bit
mov ah, cl
ror ax, 8
mov $pc, eax
jmp PollInt
ALIGNXMM
noCrossPage:
call CpuAMreadW@4
mov $pc, eax
jmp PollInt
;***
; JSR 20: ABS 6 cycles
;
;
; Algorithm:
;
; PC--;
; PUSH((PC >> 8) & 0xff); /* Push return address onto the stack. */
; PUSH(PC & 0xff);
; PC = (src);
;
;*************************************************
OP20: ; JSR
movzx eax, wot[edi+1]
mov ecx, $s
mov esi, $ct
and ecx, 255
mov edx, $pc
add dx, 1
nop
add esi, 6
mov $pc, eax
mov wot[ram+0100h+ecx-1], dx
nop
sub cl, 2
nop
mov $s, ecx
mov $ct, esi
jmp PollInt
;***
; RTI 40
;
;
; Algorithm:
;
; src = PULL();
; SET_SR(src);
; src = PULL();
; src |= (PULL() << 8); /* Load return address from stack. */
; PC = (src);
;
;*************************************************
OP40: ; RTI
mov ecx, $s
mov esi, $ct
and ecx, 255
add esi, 6
add cl, 3
nop
mov al, byt[ram+0100h+ecx-2]
nop
mov dx, wot[ram+0100h+ecx-1]
nop
mov $s, ecx
mov $p, eax
mov $ct, esi
mov $pc, edx
jmp PollInt
;***
; RTS 60
;
;
; Algorithm:
;
; src = PULL();
; src += ((PULL()) << 8) + 1; /* Load return address from stack and add 1. */
; PC = (src);
;
;*************************************************
OP60: ; RTS
mov ecx, $s
mov esi, $ct
and ecx, 255
add esi, 6
add cl, 2
nop
mov dx, wot[ram+0100h+ecx-1]
nop
add dx, 1
nop
mov $s, ecx
nop
mov $ct, esi
mov $pc, edx
jmp PollInt
PSW.asm
; d7 - d0: N V R B D I Z C
OP18: ; CLC 0001 index:0
mov eax, $p
mov ecx, $ct
and eax, 11111110b
add ecx, 2
mov $p, eax
mov $ct, ecx
jmp PollInt
OPD8: ; CLD 1101 index:6
mov eax, $p
mov ecx, $ct
and eax, 11110111b
add ecx, 2
mov $p, eax
mov $ct, ecx
jmp PollInt
OP58: ; CLI 1001 index:4
mov eax, $p
mov ecx, $ct
and eax, 11111011b
add ecx, 2
mov $p, eax
mov $ct, ecx
jmp PollInt
OPB8: ; CLV 1011 index:5
mov eax, $p
mov ecx, $ct
and eax, 10111111b
add ecx, 2
mov $p, eax
mov $ct, ecx
jmp PollInt
OP38: ; SEC 0011 index:1
mov eax, $p
mov ecx, $ct
or eax, 00000001b
add ecx, 2
mov $p, eax
mov $ct, ecx
jmp PollInt
OPF8: ; SED 1111 index:7
mov eax, $p
mov ecx, $ct
or eax, 00001000b
add ecx, 2
mov $p, eax
mov $ct, ecx
jmp PollInt
OP78: ; SEI 0111 index:3
mov eax, $p
mov ecx, $ct
or eax, 00000100b
add ecx, 2
mov $p, eax
mov $ct, ecx
jmp PollInt
READ.asm
;***
; LDA
; A9: ACC 2 cycles
; A5: ZERO PAGE 3 cycles
; B5: ZERO PAGE X 4 cycles
; AD: ABS 4 cycles
; BD: ABS X 4 cycles (test cross page)
; B9: ABS Y 4 cycles (test cross page)
; A1: X INDIRECT 6 cycles
; B1: INDIRECT Y 5 cycles (test cross page)
; X A5: X REG 2 cycles
; X A6: ZERO PAGE 3 cycles
; X B6: ZERO PAGE Y 4 cycles
; X AE: ABS 4 cycles
; X BE: ABS Y 4 cycles (test cross page)
; Y A0: Y REG 2 cycles
; Y A4: ZERO PAGE 3 cycles
; Y B4: ZERO PAGE X 4 cycles
; Y AC: ABS 4 cycles
; Y BC: ABS X 4 cycles (test cross page)
;
; Algorithm:
;
; SET_SIGN(src);
; SET_ZERO(src);
; AC = (src);
;
;*************************************************
OPA9: ; LDA #$
movzx eax, byt[edi+1]
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1 ; opcode nums
and ecx, 07Dh
add esi, 2 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPA5: ; LDA ZERO PAGE
movzx eax, byt[edi+1]
movzx eax, byt[ram+eax]
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1
and ecx, 07Dh
add esi, 3
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPB5: ; LDA ZERO PAGE X
mov ecx, $x
and ecx, 255
movzx eax, byt[edi+1]
add al, cl
movzx eax, byt[ram+eax]
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1
and ecx, 07Dh
add esi, 4
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPAD: ; LDA ABS
movzx eax, wot[edi+1]
push eax
call CpuAMread@4
and eax, 255
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 2 ; opcode nums
and ecx, 07Dh
add esi, 4 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPBD: ; LDA ABS X
movzx eax, wot[edi+1]
mov ecx, $x
and ecx, 0FFh
add cx, ax
cmp ah, ch
adc $ct, 0
push ecx
call CpuAMread@4
and eax, 255
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 2 ; opcode nums
and ecx, 07Dh
add esi, 4 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPB9: ; LDA ABS Y
movzx eax, wot[edi+1]
mov ecx, $y
and ecx, 0FFh
add cx, ax
cmp ah, ch
adc $ct, 0
push ecx
call CpuAMread@4
and eax, 255
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 2 ; opcode nums
and ecx, 07Dh
add esi, 4 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPA1: ; LDA X INDIRECT
movzx eax, byt[edi+1]
mov ecx, $x
and ecx, 255
add cl , al
movzx eax, wot[ram+ecx]
push eax
call CpuAMread@4
and eax, 255
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1 ; opcode nums
and ecx, 07Dh
add esi, 6 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPB1: ; LDA ($??),Y
movzx eax, byt[edi+1]
movzx eax, wot[ram+eax]
mov ecx, $y
and ecx, 0FFh
add cx, ax
cmp ah, ch
adc $ct, 0
push ecx
call CpuAMread@4
and eax, 255
mov $a, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1 ; opcode nums
and ecx, 07Dh
add esi, 5 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPA2: ; LDX #$
movzx eax, byt[edi+1]
mov $x, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1 ; opcode nums
and ecx, 07Dh
add esi, 2 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPA6: ; LDX ZERO PAGE
movzx eax, byt[edi+1]
movzx eax, byt[ram+eax]
mov $x, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1
and ecx, 07Dh
add esi, 3
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPB6: ; LDX ZERO PAGE Y
mov ecx, $y
and ecx, 255
movzx eax, byt[edi+1]
add al, cl
movzx eax, byt[ram+eax]
mov $x, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1
and ecx, 07Dh
add esi, 4
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPAE: ; LDX ABS
movzx eax, wot[edi+1]
push eax
call CpuAMread@4
and eax, 255
mov $x, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 2 ; opcode nums
and ecx, 07Dh
add esi, 4 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPBE: ; LDX ABS Y
movzx eax, wot[edi+1]
mov ecx, $y
and ecx, 0FFh
add cx, ax
cmp ah, ch
adc $ct, 0
push ecx
call CpuAMread@4
and eax, 255
mov $x, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 2 ; opcode nums
and ecx, 07Dh
add esi, 4 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPA0: ; LDY #$
movzx eax, byt[edi+1]
mov $y, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1 ; opcode nums
and ecx, 07Dh
add esi, 2 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPA4: ; LDY ZERO PAGE
movzx eax, byt[edi+1]
movzx eax, byt[ram+eax]
mov $y, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1
and ecx, 07Dh
add esi, 3
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPB4: ; LDY ZERO PAGE X
mov ecx, $x
and ecx, 255
movzx eax, byt[edi+1]
add al, cl
movzx eax, byt[ram+eax]
mov $y, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 1
and ecx, 07Dh
add esi, 4
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPAC: ; LDY ABS
movzx eax, wot[edi+1]
push eax
call CpuAMread@4
and eax, 255
mov $y, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 2 ; opcode nums
and ecx, 07Dh
add esi, 4 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
OPBC: ; LDY ABS X
movzx eax, wot[edi+1]
mov ecx, $x
and ecx, 0FFh
add cx, ax
cmp ah, ch
adc $ct, 0
push ecx
call CpuAMread@4
and eax, 255
mov $y, eax
mov edx, $pc
mov esi, $ct
mov ecx, $p
add edx, 2 ; opcode nums
and ecx, 07Dh
add esi, 4 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, esi
mov $p, ecx
mov $pc, edx
nop
jmp PollInt
RTOR.asm
; trans REG to REG
; tXN
; X source REG
; N target REG
; TXS not set Z-N flag (only this.. other must set Z-N flag)...
; cycles all 2 cycles ...
OPAA: ; TAX
mov eax, $a
mov ecx, $p
and ecx, 07Dh
mov $x, eax
and eax, 255
mov edx, $ct
or ecx, dwot[zn_t+eax*4]
add edx, 2
mov $p, ecx
mov $ct, edx
jmp PollInt
OP8A: ; TXA
mov eax, $x
mov ecx, $p
and ecx, 07Dh
mov $a, eax
and eax, 255
mov edx, $ct
or ecx, dwot[zn_t+eax*4]
add edx, 2
mov $p, ecx
mov $ct, edx
jmp PollInt
OPA8: ; TAY
mov eax, $a
mov ecx, $p
and ecx, 07Dh
mov $y, eax
and eax, 255
mov edx, $ct
or ecx, dwot[zn_t+eax*4]
add edx, 2
mov $p, ecx
mov $ct, edx
jmp PollInt
OP98: ; TYA
mov eax, $y
mov ecx, $p
and ecx, 07Dh
mov $a, eax
and eax, 255
mov edx, $ct
or ecx, dwot[zn_t+eax*4]
add edx, 2
mov $p, ecx
mov $ct, edx
jmp PollInt
OPBA: ; TSX
mov eax, $s
mov ecx, $p
and ecx, 07Dh
mov $x, eax
and eax, 255
mov edx, $ct
or ecx, dwot[zn_t+eax*4]
add edx, 2
mov $p, ecx
mov $ct, edx
jmp PollInt
OP9A: ; TXS (RTOR only this not set flag)
mov eax, $x
mov edx, $ct
mov $s, eax
add edx, 2
nop
mov $ct, edx
jmp PollInt
SHIFT.asm
;***
; ASL
; 0A: ACC 2 cycles
; 06: ZERO PAGE 5 cycles
; 16: ZERO PAGE X 6 cycles
; 0E: ABS 6 cycles
; 1E: ABS X 7 cycles
; Algorithm:
;
; SET_CARRY(src & 0x80);
; src <<= 1;
; src &= 0xff;
; SET_SIGN(src);
; SET_ZERO(src);
; STORE src in memory or accumulator depending on addressing mode.
;
;*************************************************
OP0A: ; ASL A
mov eax, $a ; - U load acc
mov ecx, $p ; - V load flag
and eax, 11111111b ; - U clear other bit
and ecx, 01111100b ; - V clear N-Z-C flag
shl al, 1 ; - U ASL opr
nop ; - V spare
adc ecx, 0 ; - U reset C flag
mov edx, $ct ; - V load cycles cnt
mov $a, eax ; - U write back acc (eax free)
add edx, 2 ; - V 2 cycles
or ecx, dwot[zn_t+eax*4] ; - U reset Z-N flags
mov $ct, edx ; - V write back cycles cnt (edx free)
mov $p, ecx ; - U write back flag (ecx free)
jmp PollInt
OP06: ; ASL ZERO PAGE
movzx esi, byt[edi+1] ; - N load zero page inx
movzx eax, byt[ram+esi] ; - N load val
mov ecx, $p ; - U load flag
mov edx, $pc ; - V load PC
and ecx, 01111100b ; - U clear N-Z-C flag
inc edx ; - V ++ PC
shl al, 1 ; - U ASL opr
nop ; - V spare
adc ecx, 0 ; - U reset C flag
mov edi, $ct ; - V load cycles cnt
mov byt[esi+ram], al ; - U write back acc (free eax)
or cl, byt[zn_t+eax*4] ; - V reset N-Z flag
mov $p, ecx ; - U write back flag (ecx free)
add edi, 5 ; - V 5 cycles
mov $ct, edi
mov $pc, edx
jmp PollInt
OP16: ; ASL ZERO PAGE X
movzx esi, byt[edi+1] ; - N load zero page inx
add esi, $x
nop
and esi, 11111111b
nop
movzx eax, byt[ram+esi] ; - N load val
mov ecx, $p ; - U load flag
mov edx, $pc ; - V load PC
and ecx, 01111100b ; - U clear N-Z-C flag
inc edx ; - V ++ PC
shl al, 1 ; - U ASL opr
nop ; - V spare
adc ecx, 0 ; - U reset C flag
mov edi, $ct ; - V load cycles cnt
mov byt[esi+ram], al ; - U write back acc (free eax)
or cl, byt[zn_t+eax*4] ; - V reset N-Z flag
mov $p, ecx ; - U write back flag (ecx free)
add edi, 6 ; - V 6 cycles
mov $ct, edi ;
mov $pc, edx
jmp PollInt
OP0E: ; ASL ABS
movzx esi, wot[edi+1] ; - N load abs inx
push esi ; - U
mov edi, $ct ; - V
call CpuAMread@4
mov edx, $p ; - U load val
and eax, 11111111b ; - V
add edi, 6 ; - U 6 cycles
and edx, 01111100b ; - V clear Z-N-C flag
shl al, 1 ; - U ASL opr
nop ; - V spare
adc edx, 0 ; - U reset C flag
mov ecx, $pc ; - V load PC
or edx, dwot[zn_t+eax*4]
add ecx, 2 ; - V ++ PC
mov $ct, edi ; - U write back cycles cnt (edi free)
mov $pc, ecx ; - V write back PC (ecx free)
push eax
push esi
mov $p, edx ; - U
nop
call CpuAMwrite@8
jmp PollInt
OP1E: ; ASL ABS X
movzx esi, wot[edi+1] ; - N load abs inx
movzx ecx, byt[ebx+4]
add si, cx
nop
push esi ; - U
mov edi, $ct ; - V
call CpuAMread@4
mov edx, $p ; - U load val
and eax, 11111111b ; - V
add edi, 7 ; - U 7 cycles
and edx, 01111100b ; - V clear Z-N-C flag
shl al, 1 ; - U ASL opr
nop ; - V spare
adc edx, 0 ; - U reset C flag
mov ecx, $pc ; - V load PC
or edx, dwot[zn_t+eax*4]
add ecx, 2 ; - V ++ PC
mov $ct, edi ; - U write back cycles cnt (edi free)
mov $pc, ecx ; - V write back PC (ecx free)
push eax
push esi
mov $p, edx ; - U
nop
call CpuAMwrite@8
jmp PollInt
;***
; LSR
; 4A: ACC 2 cycles
; 46: ZERO PAGE 5 cycles
; 56: ZERO PAGE X 6 cycles
; 4E: ABS 6 cycles
; 5E: ABS X 7 cycles
; Algorithm:
;
; SET_CARRY(src & 0x01);
; src >>= 1;
; SET_SIGN(src);
; SET_ZERO(src);
; STORE src in memory or accumulator depending on addressing mode.
;
;*************************************************
OP4A: ; LSR A
mov eax, $a ; - U load acc
mov ecx, $p ; - V load flag
and eax, 11111111b ; - U clear other bit
and ecx, 01111100b ; - V clear N-Z-C flag
shr eax, 1 ; - U LSR opr
mov edx, $ct ; - V load cycles cnt
adc ecx, 0 ; - U reset C flag
add edx, 2 ; - V 2 cycles
mov $a, eax ; - U write back acc (eax free)
or ecx, dwot[zn_t+eax*4] ; - V reset Z-N flags
mov $p, ecx ; - U write back flag (ecx free)
mov $ct, edx ; - V write back cycles cnt (edx free)
jmp PollInt
OP46: ; LSR ZERO PAGE
movzx esi, byt[edi+1] ; - N load zero page inx
movzx eax, byt[ram+esi] ; - N load val
mov ecx, $p ; - U load flag
mov edx, $pc ; - V load PC
and ecx, 01111100b ; - U clear N-Z-C flag
inc edx ; - V ++ PC
shr eax, 1 ; - U LSR opr
nop ; - V spare
adc ecx, 0 ; - U reset C flag
mov edi, $ct ; - V load cycles cnt
mov byt[esi+ram], al ; - U write back acc (free eax)
or cl, byt[zn_t+eax*4] ; - V reset N-Z flag
mov $p, ecx ; - U write back flag (ecx free)
add edi, 5 ; - V 5 cycles
mov $ct, edi
mov $pc, edx
jmp PollInt
OP56: ; LSR ZERO PAGE X
movzx esi, byt[edi+1] ; - N load zero page inx
add esi, $x
nop
and esi, 11111111b
nop
movzx eax, byt[ram+esi] ; - N load val
mov ecx, $p ; - U load flag
mov edx, $pc ; - V load PC
and ecx, 01111100b ; - U clear N-Z-C flag
inc edx ; - V ++ PC
shr eax, 1 ; - U LSR opr
nop ; - V spare
adc ecx, 0 ; - U reset C flag
mov edi, $ct ; - V load cycles cnt
mov byt[esi+ram], al ; - U write back acc (free eax)
or cl, byt[zn_t+eax*4] ; - V reset N-Z flag
mov $p, ecx ; - U write back flag (ecx free)
add edi, 6 ; - V 6 cycles
mov $ct, edi ;
mov $pc, edx
jmp PollInt
OP4E: ; LSR ABS
movzx esi, wot[edi+1] ; - N load abs inx
push esi ; - U
mov edi, $ct ; - V
call CpuAMread@4
mov edx, $p ; - U load val
and eax, 11111111b ; - V
add edi, 6 ; - U 6 cycles
and edx, 01111100b ; - V clear Z-N-C flag
shr eax, 1 ; - U LSR opr
nop ; - V spare
adc edx, 0 ; - U reset C flag
mov ecx, $pc ; - V load PC
or edx, dwot[zn_t+eax*4]
add ecx, 2 ; - V ++ PC
mov $ct, edi ; - U write back cycles cnt (edi free)
mov $pc, ecx ; - V write back PC (ecx free)
push eax
push esi
mov $p, edx ; - U
nop
call CpuAMwrite@8
jmp PollInt
OP5E: ; LSR ABS X
movzx esi, wot[edi+1] ; - N load abs inx
movzx ecx, byt[ebx+4]
add si, cx
nop
push esi ; - U
mov edi, $ct ; - V
call CpuAMread@4
mov edx, $p ; - U load val
and eax, 11111111b ; - V
add edi, 7 ; - U 7 cycles
and edx, 01111100b ; - V clear Z-N-C flag
shr eax, 1 ; - U LSR opr
nop ; - V spare
adc edx, 0 ; - U reset C flag
mov ecx, $pc ; - V load PC
or edx, dwot[zn_t+eax*4]
add ecx, 2 ; - V ++ PC
mov $ct, edi ; - U write back cycles cnt (edi free)
mov $pc, ecx ; - V write back PC (ecx free)
push eax
push esi
mov $p, edx ; - U
nop
call CpuAMwrite@8
jmp PollInt
;***
; ROL
; 2A: ACC 2 cycles
; 26: ZERO PAGE 5 cycles
; 36: ZERO PAGE X 6 cycles
; 2E: ABS 6 cycles
; 3E: ABS X 7 cycles
; Algorithm:
;
; src <<= 1;
; if (IF_CARRY()) {
; src |= 0x1;
; }
; SET_CARRY(src > 0xff);
; src &= 0xff;
; SET_SIGN(src);
; SET_ZERO(src);
; STORE src in memory or accumulator depending on addressing mode.
;
;*************************************************
OP2A: ; ROL A
mov eax, $a
mov ecx, $p
and eax, 11111111b
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcl al, 1 ; 2a03 rol opr ... with old c
rcl cl, 1
nop
mov edx, $ct
nop
mov $a, eax
add edx, 2 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
jmp PollInt
OP26: ; ROL ZERO PAGE
movzx esi, byt[edi+1]
movzx eax, byt[ram+esi]
mov ecx, $p
nop
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcl al, 1 ; 2a03 rol opr ... with old c
rcl cl, 1
add edx, 1
mov $pc, edx
mov edx, $ct
mov byt[esi+ram], al
add edx, 5 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
jmp PollInt
OP36: ; ROL ZERO PAGE X
movzx esi, byt[edi+1]
add esi, $x
and esi, 11111111b
movzx eax, byt[ram+esi]
mov ecx, $p
nop
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcl al, 1 ; 2a03 rol opr ... with old c
rcl cl, 1
add edx, 1
mov $pc, edx
mov edx, $ct
mov byt[esi+ram], al
add edx, 6 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
jmp PollInt
OP2E: ; ROL ABS
movzx esi, wot[edi+1]
push esi
nop
call CpuAMread@4
and eax, 11111111b
mov ecx, $p
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcl al, 1 ; 2a03 rol opr ... with old c
rcl cl, 1
add edx, 2
mov $pc, edx
mov edx, $ct
add edx, 6 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
push eax
push esi
call CpuAMwrite@8
jmp PollInt
OP3E: ; ROL ABS X
movzx esi, wot[edi+1]
movzx ecx, byt[ebx+4]
add esi, ecx
push esi
nop
call CpuAMread@4
and eax, 11111111b
mov ecx, $p
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcl al, 1 ; 2a03 rol opr ... with old c
rcl cl, 1
add edx, 2
mov $pc, edx
mov edx, $ct
add edx, 7 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
push eax
push esi
call CpuAMwrite@8
jmp PollInt
;***
; ROR
; 6A: ACC 2 cycles
; 66: ZERO PAGE 5 cycles
; 76: ZERO PAGE X 6 cycles
; 6E: ABS 6 cycles
; 7E: ABS X 7 cycles
; Algorithm:
;
; if (IF_CARRY()) {
; src |= 0x100;
; }
; SET_CARRY(src & 0x01);
; src >>= 1;
; SET_SIGN(src);
; SET_ZERO(src);
; STORE src in memory or accumulator depending on addressing mode.
;
;*************************************************
OP6A: ; ROR A
mov eax, $a
mov ecx, $p
and eax, 11111111b
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcr al, 1 ; 2a03 ror opr ... with old c
rcl cl, 1
nop
mov edx, $ct
nop
mov $a, eax
add edx, 2 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
jmp PollInt
OP66: ; ROR ZERO PAGE
movzx esi, byt[edi+1]
movzx eax, byt[ram+esi]
mov ecx, $p
nop
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcr al, 1 ; 2a03 ror opr ... with old c
rcl cl, 1
add edx, 1
mov $pc, edx
mov edx, $ct
mov byt[esi+ram], al
add edx, 5 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
jmp PollInt
OP76: ; ROR ZERO PAGE X
movzx esi, byt[edi+1]
add esi, $x
and esi, 11111111b
movzx eax, byt[ram+esi]
mov ecx, $p
nop
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcr al, 1 ; 2a03 ror opr ... with old c
rcl cl, 1
add edx, 1
mov $pc, edx
mov edx, $ct
mov byt[esi+ram], al
add edx, 6 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
jmp PollInt
OP6E: ; ROR ABS
movzx esi, wot[edi+1]
push esi
nop
call CpuAMread@4
and eax, 11111111b
mov ecx, $p
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcr al, 1 ; 2a03 ror opr ... with old c
rcl cl, 1
add edx, 2
mov $pc, edx
mov edx, $ct
add edx, 6 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
push eax
push esi
call CpuAMwrite@8
jmp PollInt
OP7E: ; ROR ABS X
movzx esi, wot[edi+1]
movzx ecx, byt[ebx+4]
add esi, ecx
push esi
nop
call CpuAMread@4
and eax, 11111111b
mov ecx, $p
mov edx, $pc
and ecx, 01111101b ; save C flag
shr cl, 1 ; into x86's C flag
rcr al, 1 ; 2a03 ror opr ... with old c
rcl cl, 1
add edx, 2
mov $pc, edx
mov edx, $ct
add edx, 7 ; cycles
or ecx, dwot[zn_t+eax*4]
mov $ct, edx
mov $p, ecx
push eax
push esi
call CpuAMwrite@8
jmp PollInt
BRK.asm
OP00:
OPEA:
; When the MOS 6502 processor was modified into the Ricoh 2A03 chip for the NES,\
; the BRK (Force Break) opcode was eliminated.
; Thus, the BRK command doesn't actually do anything on the NES and is effectively identical to NOP.
; Because of this, when you see a BRK in decompiled NES code,\
; you can be fairly certain that the #00 value is either game data or unused.
; Having a BRK execute on the NES won't harm anything, it will only eat up a clock cycle to process.
; You can take advantage of this feature when making game cheats.
; For example, if you want to change an opcode that takes a two-byte operand into an opcode that uses a one-byte operand,\
; you can ignore the second byte of the operand if it is a #00 because the NES will simply treat it as a BRK, which is ignored.
; On an original MOS 6502 processor,\
; BRK would set the Interrupt Flag to prevent further interrupts and then move the Program Counter Register to the new location.
; Addressing Modes
; ==================================================================
; Addressing Mode Assembly Language Form Opcode # Bytes # Cycles
; =============== ====================== ====== ====== =====
; Implied BRK 00 1 2
; ========================================================================
; ref link: www.thealmightyguru.com/Games/Hacking/Wiki/index.php?title=BRK
; ========================================================================
add $ct, 2
jmp PollInt
STACK.asm
OP48: ; PHA
mov eax, $a
mov edx, $s
and edx, 255
mov ecx, $ct
mov byt[ram+0100h+edx], al
sub dl, 1
add ecx, 3
nop
mov $ct, ecx
mov $s, edx
jmp PollInt
OP08: ; PHP
mov eax, $p
mov edx, $s
and edx, 255
mov ecx, $ct
or eax, B_FLAG
nop
mov byt[ram+0100h+edx], al
sub dl, 1
add ecx, 3
nop
mov $ct, ecx
mov $s, edx
jmp PollInt
OP68: ; PLA
mov ecx, $p
mov edx, $s
and ecx, 07Dh ; clr z-n flag
and edx, 255
mov al, byt[ram+0101h+edx]
add dl, 1
and eax, 255
mov $s, edx
mov esi, $ct
mov $a, eax
or ecx, dwot[zn_t+eax*4]
add esi, 4
mov $p, ecx
mov $ct, esi
jmp PollInt
OP28: ; PLP
mov edx, $s
nop
and edx, 255
nop
mov al, byt[ram+0101h+edx]
add dl, 1
mov $s, edx
mov esi, $ct
add esi, 4
mov $p, eax
nop
mov $ct, esi
jmp PollInt
TEST.asm
;***
; BIT
; 24: ZERO PAGE 3 cycles
; 2C: ABS 4 cycles
; Algorithm:
;
; SET_SIGN(src);
; SET_OVERFLOW(0x40 & src);
; SET_ZERO(src & AC);
;*************************************************
OP24: ; BIT ZERO PAGE 3 cycles
movzx eax, byt[edi+1]
mov al, byt[ram+eax]
nop
mov esi, $ct
mov edx, $p
and edx, 00111101b
mov ecx, eax
and eax, 0C0h
add esi, 3
or edx, eax
mov eax, $a
and al, cl
setz cl
lea edx, [edx+ecx*2]
mov eax, $pc
mov $ct, esi
add eax, 1
mov $p, edx
mov $pc, eax
jmp PollInt
OP2C: ; BIT ABS 4 cycles
movzx eax, wot[edi+1]
push eax
nop
call CpuAMread@4
and eax, 255
nop
mov esi, $ct
mov edx, $p
and edx, 00111101b
mov ecx, eax
and eax, 0C0h
add esi, 4
or edx, eax
mov eax, $a
and al, cl
setz cl
lea edx, [edx+ecx*2]
mov eax, $pc
mov $ct, esi
add eax, 2
mov $p, edx
mov $pc, eax
jmp PollInt
WRITE.asm
;***
; STA
; 85: ZERO PAGE 3 cycles
; 95: ZERO PAGE X 4 cycles
; 80: ABS 4 cycles
; 90: ABS X 5 cycles
; 99: ABS Y 5 cycles
; 81: X INDIRECT 6 cycles
; 91: INDIRECT Y 6 cycles (no test cross page)
; X 86: ZERO PAGE 3 cycles
; X 96: ZERO PAGE Y 4 cycles
; X 8E: ABS 4 cycles
; Y 84: ZERO PAGE 3 cycles
; Y 94: ZERO PAGE X 4 cycles
; Y 8C: ABS 4 cycles
;
; Algorithm:
;
; STORE(address, A);
;
;*************************************************
OP85: ; STA ZERO PAGE
movzx eax, byt[edi+1]
mov ecx, $ct
mov edx, $a
mov byt[ram+eax], dl
mov eax, $pc
add eax, 1
add ecx, 3
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP95: ; STA ZERO PAGE X
movzx eax, byt[edi+1]
add eax, $x
mov ecx, $ct
and eax, 255
mov edx, $a
mov byt[ram+eax], dl
mov eax, $pc
add eax, 1
add ecx, 4
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP8D: ; STA ABS
movzx eax, wot[edi+1]
push $a
push eax
call CpuAMwrite@8
mov ecx, $ct
mov eax, $pc
add eax, 2
add ecx, 4
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP9D: ; STA ABS X
movzx eax, wot[edi+1]
mov ecx, $x
and ecx, 0FFh
nop
add eax, ecx
nop
push $a
push eax
call CpuAMwrite@8
mov ecx, $ct
mov eax, $pc
add eax, 2
add ecx, 5
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP99: ; STA ABS Y
movzx eax, wot[edi+1]
mov ecx, $y
and ecx, 0FFh
nop
add eax, ecx
nop
push $a
push eax
call CpuAMwrite@8
mov ecx, $ct
mov eax, $pc
add eax, 2
add ecx, 5
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP81: ; STA X INDIRECT
movzx eax, byt[edi+1]
mov ecx, $x
add al, cl
nop
mov ax, wot[eax+ram]
nop
push $a
push eax
call CpuAMwrite@8
mov ecx, $ct
mov eax, $pc
add eax, 1
add ecx, 6
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP91: ; STA INDIRECT Y
movzx eax, byt[edi+1]
movzx eax, wot[eax+ram]
mov ecx, $y
and ecx, 0FFh
add ax, cx
nop
push $a
push eax
call CpuAMwrite@8
mov ecx, $ct
mov eax, $pc
add eax, 1
add ecx, 6
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP86: ; STX ZERO PAGE
movzx eax, byt[edi+1]
mov ecx, $ct
mov edx, $x
mov byt[ram+eax], dl
mov eax, $pc
add eax, 1
add ecx, 3
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP96: ; STX ZERO PAGE Y
movzx eax, byt[edi+1]
add eax, $y
mov ecx, $ct
and eax, 255
mov edx, $x
mov byt[ram+eax], dl
mov eax, $pc
add eax, 1
add ecx, 4
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP8E: ; STX ABS
movzx eax, wot[edi+1]
push $x
push eax
call CpuAMwrite@8
mov ecx, $ct
mov eax, $pc
add eax, 2
add ecx, 4
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP84: ; STY ZERO PAGE
movzx eax, byt[edi+1]
mov ecx, $ct
mov edx, $y
mov byt[ram+eax], dl
mov eax, $pc
add eax, 1
add ecx, 3
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP94: ; STY ZERO PAGE X
movzx eax, byt[edi+1]
add eax, $x
mov ecx, $ct
and eax, 255
mov edx, $y
mov byt[ram+eax], dl
mov eax, $pc
add eax, 1
add ecx, 4
mov $pc, eax
mov $ct, ecx
jmp PollInt
OP8C: ; STY ABS
movzx eax, wot[edi+1]
push $y
push eax
call CpuAMwrite@8
mov ecx, $ct
mov eax, $pc
add eax, 2
add ecx, 4
mov $pc, eax
mov $ct, ecx
jmp PollInt
REMAIN.asm
OP02:
OP03:
OP04:
OP07:
OP0B:
OP0C:
OP0F:
OP12:
OP13:
OP14:
OP17:
OP1A:
OP1B:
OP1C:
OP1F:
OP22:
OP23:
OP27:
OP2B:
OP2F:
OP32:
OP33:
OP34:
OP37:
OP3A:
OP3B:
OP3C:
OP3F:
OP42:
OP43:
OP44:
OP47:
OP4B:
OP4F:
OP52:
OP53:
OP54:
OP57:
OP5A:
OP5B:
OP5C:
OP5F:
OP62:
OP63:
OP64:
OP67:
OP6B:
OP6F:
OP72:
OP73:
OP74:
OP77:
OP7A:
OP7B:
OP7C:
OP7F:
OP80:
OP82:
OP83:
OP87:
OP89:
OP8B:
OP8F:
OP92:
OP93:
OP97:
OP9B:
OP9C:
OP9E:
OP9F:
OPA3:
OPA7:
OPAB:
OPAF:
OPB2:
OPB3:
OPB7:
OPBB:
OPBF:
OPC2:
OPC3:
OPC7:
OPCB:
OPCF:
OPD2:
OPD3:
OPD4:
OPD7:
OPDA:
OPDB:
OPDC:
OPDF:
OPE2:
OPE3:
OPE7:
OPEB:
OPEF:
OPF2:
OPF3:
OPF4:
OPF7:
OPFA:
OPFB:
OPFC:
OPFF:
int 3
ALIGNXMM
OPTAB dd OP00, OP01, OP02, OP03, OP04, OP05, OP06, OP07, OP08, OP09, OP0A, OP0B, OP0C, OP0D, OP0E, OP0F
dd OP10, OP11, OP12, OP13, OP14, OP15, OP16, OP17, OP18, OP19, OP1A, OP1B, OP1C, OP1D, OP1E, OP1F
dd OP20, OP21, OP22, OP23, OP24, OP25, OP26, OP27, OP28, OP29, OP2A, OP2B, OP2C, OP2D, OP2E, OP2F
dd OP30, OP31, OP32, OP33, OP34, OP35, OP36, OP37, OP38, OP39, OP3A, OP3B, OP3C, OP3D, OP3E, OP3F
dd OP40, OP41, OP42, OP43, OP44, OP45, OP46, OP47, OP48, OP49, OP4A, OP4B, OP4C, OP4D, OP4E, OP4F
dd OP50, OP51, OP52, OP53, OP54, OP55, OP56, OP57, OP58, OP59, OP5A, OP5B, OP5C, OP5D, OP5E, OP5F
dd OP60, OP61, OP62, OP63, OP64, OP65, OP66, OP67, OP68, OP69, OP6A, OP6B, OP6C, OP6D, OP6E, OP6F
dd OP70, OP71, OP72, OP73, OP74, OP75, OP76, OP77, OP78, OP79, OP7A, OP7B, OP7C, OP7D, OP7E, OP7F
dd OP80, OP81, OP82, OP83, OP84, OP85, OP86, OP87, OP88, OP89, OP8A, OP8B, OP8C, OP8D, OP8E, OP8F
dd OP90, OP91, OP92, OP93, OP94, OP95, OP96, OP97, OP98, OP99, OP9A, OP9B, OP9C, OP9D, OP9E, OP9F
dd OPA0, OPA1, OPA2, OPA3, OPA4, OPA5, OPA6, OPA7, OPA8, OPA9, OPAA, OPAB, OPAC, OPAD, OPAE, OPAF
dd OPB0, OPB1, OPB2, OPB3, OPB4, OPB5, OPB6, OPB7, OPB8, OPB9, OPBA, OPBB, OPBC, OPBD, OPBE, OPBF
dd OPC0, OPC1, OPC2, OPC3, OPC4, OPC5, OPC6, OPC7, OPC8, OPC9, OPCA, OPCB, OPCC, OPCD, OPCE, OPCF
dd OPD0, OPD1, OPD2, OPD3, OPD4, OPD5, OPD6, OPD7, OPD8, OPD9, OPDA, OPDB, OPDC, OPDD, OPDE, OPDF
dd OPE0, OPE1, OPE2, OPE3, OPE4, OPE5, OPE6, OPE7, OPE8, OPE9, OPEA, OPEB, OPEC, OPED, OPEE, OPEF
dd OPF0, OPF1, OPF2, OPF3, OPF4, OPF5, OPF6, OPF7, OPF8, OPF9, OPFA, OPFB, OPFC, OPFD, OPFE, OPFF