FPGA之硬件描述语言Verilog 中 if和case语句的区别

在Asic 设计过程中，硬件语言的描述方式直接影响着模块的工作效率，if和case语句是常在时序电路中用到的语言，本文将用两中不同的语句来实现同一种功能，通过RTL、实现后的原理图、资源消耗做一个综合对比

1 两种if语句的实现方式
代码如下

module com_if1(
    clk,
    rst,
    en,
    led
    );
    input clk;
    input rst;
    input en;
    output reg [2:0]led;

    reg ready;
    always @ (posedge clk)
    if (rst)
        ready <= 0;
    else if (en)
        ready <= 1;
    else
        ready <= ready;

    reg [7:0]counter;
    always @ (posedge clk)
    if (rst)
        counter <= 0;
    else if (ready)
        counter <= counter + 1;


   always @ (posedge clk)
   if (rst)
       led <= 0;
   else if (counter == 1)
       led <= 1;
   else 
       begin
           if (counter == 2)
               led <= 2;
           else
               begin
                   if (counter == 3)
                       led <= 3;
                   else 
                        begin
                            if (counter == 4)
                                led <= 4;
                            else
                                begin
                                    if (counter == 5)
                                        led <= 5;
                                    else
                                        begin
                                            if (counter == 6)
                                                led <= 6;
                                            else
                                                led <= 7;
                                        end
                                end
                        end
               end
       end
endmodule

module com_if2(
    clk,
    rst,
    en,
    led
    );
    input clk;
    input rst;
    input en;
    output reg [2:0]led;

    reg ready;
    always @ (posedge clk)
    if (rst)
        ready <= 0;
    else if (en)
        ready <= 1;
    else
        ready <= ready;

    reg [7:0]counter;
    always @ (posedge clk)
    if (rst)
        counter <= 0;
    else if (ready)
        counter <= counter + 1;

     always @ (posedge clk)
     if (rst)
        led <= 0;
     else if (counter == 1)
        led <= 1;
     else if (counter == 2)
        led <= 2;
     else if (counter == 3 )
         led <= 3;
     else if (counter == 4)
        led <= 4;
     else if (counter == 5)
        led <= 5;
     else if (counter == 6)
        led <= 6;     
     else 
        led <= 7;
 endmodule

模块com_if1的RTL图

模块com_if2的RTL图

模块com_if1的布局布线后的原理图

模块com_if2的布局布线后的原理图

模块com_if1的资源消耗图

模块com_if2的资源消耗图

从以上几项的对比中可以发现，这种使用方法是没有区别的！！！但是第二种描述方式看起来更直观一些

2 if – else 和case的对比
case语句的代码如下

module com_case(
   clk,
   rst,
   en,
   led
   );
   input clk;
   input rst;
   input en;
   output reg [2:0]led;

   reg ready;
   always @ (posedge clk)
   if (rst)
       ready <= 0;
   else if (en)
       ready <= 1;
   else
       ready <= ready;

   reg [2:0]counter;
   always @ (posedge clk)
   if (rst)
       counter <= 0;
   else if (ready)
       counter <= counter + 1;

    always @ (posedge clk)
    if (rst)
       led <= 0;
    else 
        begin
            case(counter)
                3'd1:
                    led <= 1;
                3'd2:
                    led <= 2;
                3'd3:
                    led <= 3;
                3'd4:
                    led <= 4;
                3'd5:
                    led <= 5;
                3'd6:
                    led <= 6;
                default:led <= 7;

            endcase
        end
endmodule

模块com_if1的RTL图

模块com_case的RTL图

模块com_if1的布局布线后的原理图

模块com_case的布局布线后的原理图

模块com_if1的资源消耗图

模块com_case的资源消耗图

无论是RTL图还是布局布线后的原理图都可以看出使用case语句要简单一些，原因是case语句是以查找表的形式工作的，从图中可以看出使用case语句的最长路径要比使用if语句的要短很多，这对工程的工作频率有很大的影响；在资源消耗方面，case语句的资源消耗要少一些

综合考虑，在工程设计时，如果功能模块可以使用case语句完成，尽量使用case语句；而在使用if语句时，两种if语句的使用效果是一样的