1. M odify SBL1 first.
The calculation is 19.2*(L+(M/N))/2
//时钟计算方法
/*-----------------------------------------------------------------------*/
/* GPLL3 - BIMC PLL */
/*-----------------------------------------------------------------------*/
{
/* .eSource = */ HAL_CLK_SOURCE_GPLL3,
/* .HALConfig */ {
/* .HALConfig.eSource = */ HAL_CLK_SOURCE_XO,
/* .HALConfig.eVCO = */ HAL_CLK_PLL_VCO2,
/* .HALConfig.nPreDiv = */ 1,
/* .HALConfig.nPostDiv = */ 1,
/* .HALConfig.nL = */ 40,
// 19.2(40+(2/3))/2 780.8M
/* .HALConfig.nM = */ 2,
/* .HALConfig.nN = */ 3,
},
/* .nConfigMask = */ CLOCK_CONFIG_PLL_FSM_MODE_ENABLE,
/* .nFreqHz = */ 780800 * 1000,
/* .eVRegLevel = */ CLOCK_VREG_LEVEL_LOW,
},
修改：
-2_ap_standard_oem.git/rpm_proc/core/systemdrivers/clock/config/msm8974/ClockBSP.c
115c115
< /* .HALConfig.nL = */ 40, // 19.2(40+(2/3))/2 780.8
---
> /* .HALConfig.nL = */ 41,
120c120
<
/* .nFreqHz = */ 780800 * 1000,
---
> /* .nFreqHz = */ 800000 * 1000,
267c267
<
{ HAL_CLK_SOURCE_RAW1, { HAL_CLK_SOURCE_XO, HAL_CLK_PLL_VCO2, 1, 1, 40, 2, 3 },
CLOCK_CONFIG_PLL_FSM_MODE_ENABLE, 780800000}, /* Index = 3 */
---
> { HAL_CLK_SOURCE_RAW1, { HAL_CLK_SOURCE_XO, HAL_CLK_PLL_VCO2, 1, 1, 41, 2, 3 },
CLOCK_CONFIG_PLL_FSM_MODE_ENABLE, 800000000}, /* Index = 3 */
275,276d274
<
< nFreqHz { eSource, nDiv2x, nM, nN, n2D }, eVRegLevel
290c288
<
{ 780800000, { HAL_CLK_SOURCE_RAW1, 2, 0, 16, 0 }, CLOCK_VREG_LEVEL_HIGH, BSP_HW_VER( 0x7F, 0xFF, 0, 0), CHIPINFO_FAMILY_UNKNOWN, &BIMCPLLConfig[3] }, // AA
---
> { 800000000, { HAL_CLK_SOURCE_RAW1, 2, 0, 16, 0 }, CLOCK_VREG_LEVEL_HIGH, BSP_HW_VER( 0x7F, 0xFF, 0, 0), CHIPINFO_FAMILY_UNKNOWN, &BIMCPLLConfig[3] }, // AA
rock@VB:~/qccode/drone_source/apq8074/cs-3.0/apq8074-le-1-2_ap_standard_oem.git/rpm_proc/core/systemdrivers/clock/config/msm8974$
查看ddr频率
cat /sys/kernel/debug/clk/bimc_clk/measure
Z:\qccode\drone_source\apq8074\cs-3.0\apq8074-le-1-2_ap_standard_oem.git\r
pm_proc\core\systemdrivers\clock\hw\msm8974\ClockRPMNPA.c
显示ddr频率大小
4.1.3.1 Fix DDR frequency in RPM
This is specific to all platforms that have the RPM subsystem l ike MSM8x10, MSM8x26,
MSM8x74, MSM8x16, MSM8x39, MSM8x37, MSM8x17, MSM8x52, MSM8x76, MSM8x94,
MSM8x96, MDM9x15, MDM9x25, MSM8x40 , MSM8953, MDM9x35 , MSM8994, MSM8996,
and MSM8998.
The modification works while RPM is running :
In rpm_proc
static npa_resource_state Clock_NPANodeBIMCFunc
{
…
/* Do not scale clock if DCVS is disable. Return current speed */
pDrvCtxt = Clock_GetDrvCtxt();
if ( !pDrvCtxt- >bDCVSEnabled )
{
return pClockRsc ->pClock- >pDomain ->pBSPConfig[pClockRsc -
>nCurLevel].nFreqHz / 1000;
}
+if ( nState != 0 )
+{
+nState = 780800; //460000 is just an example, you can change to other
values but make sure this vlalue is in the BIMCClockConfig of ClockBSP.c,
the unit is khz
+}