8位非门
`timescale 1ns/10ps
module device(A,Y);
input [7:0]A;
output [7:0]Y;
assign Y=~A;
endmodule
module device_tb;
reg a;
wire y;
device device(.A(a),.Y(y));
initial begin
a<=8'h01;
#10 a<=8'h02;
#10 a<=8'h03;
#10 a<=8'h05;
#10 a<=8'h09;
#10 a<=8'h0a;
#10 a<=8'h0f;
#10 a<=8'h04;
#10 $stop;
end
endmodule
与非门
`timescale 1ns/10ps
module and_not(A,B,Y);
input A;
input B;
output Y;
assign y=~(A&B);
endmodule
module and_not_tb;
reg aa; //输入的变量都定义成reg
reg bb;
wire yy;//输出的变量定义为wire
and not and_not(.A(aa),.B(bb).Y(yy));
initial begin
aa<=0; bb<=0; //reg变量赋值的时候要使用带箭头的等号
#10 aa<=0; bb<=1;
#10 aa<=1; bb<=0;
#10 aa<=1; bb<=1;
#10 $stop;
end
endmodule
四位与非门
`timescale 1ns/10ps
module and_not_4(A,B,Y);
input [3:0] A;
input [3:0] B;
output [3:0] Y;
assign y=~(A&B);
endmodule
module and_not_4_tb;
reg [3:0] aa; //输入的变量都定义成reg
reg [3:0] bb;
wire [3:0] yy;//输出的变量定义为wire
and_not_4 and_not_4(.A(aa),.B(bb).Y(yy));
initial begin
aa<=4'b0000; bb<=4'b0000; //reg变量赋值的时候要使用带箭头的等号
#10 aa<=4'b0100; bb<=4'b0110;
#10 aa<=4'b1110; bb<=4'b0001;
#10 aa<=4'b0110; bb<=4'b0000; //注意多位的时候需要用‘
#10 $stop;
end
endmodule