创作时间：2020-11-07
目录：
Z7_DDR_pcb layout，根据ug933-Zynq-7000-PCB整理
包括以下几点
1）DDR管脚说明
2）如何接线与接线框图
2）DDR供电
4）DDR端接电阻Rterm，时钟电阻Rclk,下拉电阻Rpull_down（包括ODT电阻）
5）DDR走线长度
6）阻抗与ZQ
7）拓扑
正文：
1）Dynamic Memory (动态内存)
Zynq-7000 AP SoC devices support DDR2, DDR3/3L, and LPDDR2 (mobile DDR) dynamic
memory. The memory is connected to dedicated pins in I/O Bank 502. This bank has dedicated（专用的） I/O, termination, and reference voltage supplies.
DDR Interface Signal Pins
Table 5-4 lists all dynamic memory interface signals in Bank 502
Unused DDR pins should be connected as shown in Table 5-5.
Note: For PS_DDR_DQxx, ensure that byte lines are kept together. PS_DDR_ADDR0 should always be used. If bits must be omitted for chip select or other functionality, omit upper bit (PS_ADDR14) instead.
对于PS_DDR_DQxx，一定要保障1个byte在一起。PS_DDR_ADDR0应当一直使用。如果因为芯片选择或者其他功能，需要限制地址位的，就限制高位(PS_ADDR14)。
For designs utilizing single-ended DQS, connect the DQS signal to DQS_P. DQS_N can either be connected to the DQS_B I/O of the SDRAM, or via resistor divider to VCCO
对于采用单端DQS的设计，将DQS信号连接至DQS_P。 DQS_N也可以连接到SDRAM的DQS_B I / O，或通过电阻分压连接到VCCO/2。
Table 5-5: DDR Unused Pins
2）Dynamic Memory Implementation（实现）
Figure 5-5, Figure 5-6 and Figure 5-7 show examples of implementing DDR memory on typical boards.
3）DDR Supply Voltages 供电
Table 5-6 lists the different supply, reference and termination voltages required for
LPDDR2/DDR2/DDR3 memory.
These voltages are also required to power the DDR I/O bank,reference, and termination voltages
4）DDR Termination 终端
For better signal integrity, DDR2 and DDR3 clock, address, command and control signals need to be terminated.
为达到更好的信号完整性，DDR2 与 DDR3的时钟，地址，控制信号需要连接终端电阻（R_term）。
For DDR2, ODT and CKE are not terminated and should be pulled down during memory initialization with a 4.7 kΩ resistor to GND.
对于DDR2，ODT和CKE不需要端接（Rterm）。要保障在DDR初始化过程中，使用4.7K电阻下拉至地。
For DDR3, the DRST_B signal is not terminated an should be pulled down during memory initialization with a 4.7 kΩ resistor to GND.
对于DDR3，DRST_B 信号不需要端接（Rterm）。要保障在DDR初始化过程中，使用4.7K电阻下拉至地。
LPDDR2 does not require termination.
对于LPDDR2，不需要端接（Rterm）。
5）DDR Trace Length走线长度
All DDR memory devices should be placed as closely to the Zynq-7000 AP SoC device as possible. Table 5-8 shows the maximum recommended trace lengths for DDR signals.
In addition, DDR signals also require matched trace delays, which include package delays.
Table 5-9 shows the recommended delay matching for DDR.
Differential traces should be delay matched such that the signal crossing point occurs in the linear region of the rising and falling edges.
The skew（偏移) limits can be increased if the memory interface is not operated at the maximumfrequency, and/or if a faster memory device is utilized. See Appendix A, Processing System Memory Derating Tables for derating tables for DDR3, DDR3L, and LPDDR2.
Route the CK traces to be equal to or longer than the DQS traces per byte lane. This is
necessary because:
• The write leveling is capable of adjusting the clock to write DQS alignment over a wide
range, assuming the clock trace length is longer than the DQS traces.
• The read leveling is capable of adjusting the read data eye to read DQS over a wide
range. The adjustment is per byte, so board skew between bits (DQ,DM) should be
minimized, as indicated in Table 5-9.
• There is no automatic training for aligning command/address to clock, but a fixed
offset is programmable and can be used if necessary. Skew between CK and
address/control should be minimized, as indicated in Table 5-9.
6）DDR Trace Impedance 阻抗
All DDR signals except DDR_DRST_B require controlled impedance. DDR_CKE also requires controlled impedance in DDR3/3L. Table 5-10 shows the required trace impedance for DDR signals.
除了DDR_DRST_B管脚，DDR的所有管脚都需要进行阻抗控制。
DDR3 and LPDDR2 memory also require an additional resistor connected to the ZQ pin to calibrate the device’s output impedance. Table 5-11 shows the required RZQ values.
DDR3 和 LPDDR2还需要一个外部的电阻连接到ZQ管脚用来校准器件的输出阻抗。需要的接ZQ电阻值大小见下表5-11.
7）DDR Routing Topology拓扑
Based on the chosen memory type, the number of memory devices and layout requirements, different routing topologies can be used for DDR memory.
Figure 5-8 showsthree different topologies.三种不同的拓扑。
1）In the fly-by topology, TL0 should be 0.0-5.3 inches, with TL1 0.35-0.75 inches,
and TL20.0-1.0 inches.
在fly-by拓扑结构中，TL0应为0.0-5.3英寸，TL1为0.35-0.75英寸，TL2为0.0-1.0英寸。
注意端接电阻的位置。在最后一片DDR
2）In a point-to-point configuration the total length should be 0.0-5.3 inches. Rterm should be placed close to the load.
在点对点配置中，总长度应该是0.0-5.3英寸。 Rterm应靠近负载放置。
3）In a balanced T-branch configuration, TL0 should be 0.0-3.0 inches, with trace lengths TL1,TL2, and Tsub kept as short as possible; Rterm should be close to the intersection of TL0 andthe TL1 split.
在均衡的T型分支配置中，TL0应该为0.0-3.0英寸，并且线迹长度TL1，TL2和Tsub保持尽可能短; Rterm应接近TL0和TL1分界点的交点。
All TL1 branches must be the same electrical length and routed on the same layer.Pay attention to crosstalk-induced noise due to serpentine routing. This also applies to all TL2 branches.
所有TL1分支必须具有相同的电气长度并在同一层上布线。注意由蛇形布线引起的串扰引起的噪声。这也适用于所有TL2走线。
RECOMMENDED: Fly-by and point-to-point routing is recommended for optimal memory performance.
建议：建议使用Fly-by和点对点路由以获得最佳内存性能。
Table 5-12 shows the recommended routing topologies. Byte and bit swapping is allowed
to facilitate PCB routing, except for LPDDR2, which specifically forbids swapping. When
swapping bits, keep all bits within the same byte group.
表5-12显示了推荐的布线拓扑。除了专门禁止交换的LPDDR2外，字节和位交换是允许的以便于PCB布线。 交换位时，应注意将所有位保留在同一个字节组中。
Table 5-12: DDR Routing Topology布线拓扑
数据线没有公用，一直是“点对点”。公用的地址，控制线布线要采用T-branch或者Fly-by的拓扑来布线，具体按照表5-12推荐的拓扑来做。
THE END~