Some Cases-多位序列+时分秒计时+时钟切换

• 请实现对二进制（1011001）的序列检测功能
• 模块每拍并行输入2bit，且顺序为高位先输入
• 当检测到序列，输出一拍高电平脉冲。
• 请用Verilog描述该模块

// data[1:0]={
    
    data[1],data[0]
// data[1:0]=2'b10,则输出为01,data[0]为高位，data[1]为低位
// 考虑输入数据的复用情况，当高位满足，低位不满足时，可是可用状态

module seqdet2(
	input clk,
	input rst_n,
	input [1:0] data,
	output reg det);

//状态总数和单比特输入序列检查一致；状态转移分成1bit检测和2bit检测了；
parameter
s0=4'b000,
s1=4'b0001,
s2=4'b0010,
s3=4'b0011,
s4=4'b0100,
s5=4'b0101,
s6=4'b0110,
s7=4'b0111;

reg [3:0] state, nstate;
	
always@(posedge clk)
	if(!rst_n) state<=s0;
	else state<=nstate;

always@(*)
begin det=0; nstate=s0;
	case(state)
	s0: if(data==2'b10) nstate=s2; 
	else if(data[0]==1) nstate=s1; 
	else nstate=idle;
	s1: if(data==2'b01) nstate=s3; 
	else if(data==2'b10) nstate=s2; 
	else if(data[0]==1) nstate=s1; 
	else nstate=s0;
	s2: if(data==2'b11) nstate=s4; 
	else if(data==2'b10) nstate=s2; 
	else if(data[0]==1) nstate=s1; 
	else nstate=s0;
	s3: if(data==2'b10) nstate=s5; 
	else if(data==2'b10) nstate=s2; 
	else if(data[0]==1) nstate=s1; 
	else nstate=s0;
	s4: if(data==2'b00) nstate=s6; 
	else if(data==2'b10) nstate=s2; 
	else if(data[0]==1) nstate=s1; 
	else nstate=s0;
	s5: if(data==2'b01) nstate=s7; 
	else if(data==2'b10) nstate=s2; 
	else if(data[0]==1) nstate=s1; 
	else nstate=s0;
	s6: begin 
	if(data[1]==1) begin det=1; 
	if (data[0]==1) nstate=s1; 
	else nstate=s0; end 
	else  begin det=0; 
		if(data==2'b10) nstate=s2; 
		else if(data[0]==1) nstate=s1;
		else nstate=s0; end
			end
	s7: begin det=1;
	if(data==2'b10) nstate=s2; 
	else if(data[0]==1) nstate=s1; 
	else nstate=s0; end
	endcase
end	
endmodule	
}

• 基于100Hz的clk设计一个数字时钟，用Verilog实现以下功能

1、产生时、分、秒的计时；2、可通过3个按键来设置时、分、秒值

// 100Hz 1 clk = 0.01s
// 1 s = 100 clk，使用模100 cnt 来计1 s
module HMS(
input clk,
input rst_n,
input [5:0] hour_rst,
input [5:0] minute_rst,
input [5:0] second_rst,
output [5:0] hour,
output [5:0] minute,
output [5:0] second
);
reg [5:0] hour,minute,second;
reg [5:0] cnt;

always @(posedge clk or negedge rst_n)
if(!rst_n) cnt <= 6'b0;
else if(cnt == 99) cnt <= 6'b0;
else cnt <= cnt + 1'b1;

always @(posedge clk or negedge rst_n)
if(!rst_n) second <= second_rst;
else if((cnt == 99) && (second == 59))
		second <= 0;
else second <= second + 1'b1;

always @(posedge clk or negedge rst_n)
if(!rst_n)	minute <= minute_rst;
else if((cnt == 99)&&(second == 59))
	if(minute)
		minute <= 0;
	else
		minute <= minute + 1;

always @(posedge clk or negedge rst_n)
if(!rst_n)	hour <= hour_rst;
else(minute == 59 && second == 59 && cnt == 99)
	if(hour == 23)
		hour <= 0;
	else
		hour <= hour + 1;
		

• 有符号数的比较

module comp(
input signed [7:0]a,
input signed [7:0]b,
output c);
reg c;
always @(*)
// $signed 可综合
if($signed(a)>$signed(b))
c = 1'b1;
else
c = 1'b0;
endmodule

• 时钟切换

module clk_change(
input clk1,
input clk2,
input rst_n,
input sel,
output clk_out
);
reg clk1_dly1,clk1_dly2;
reg clk2_dly1,clk2_dly2;
reg clk1_Din,clk2_Din;

always @(*) 
if(sel) 
	clk1_Din <= sel & (~clk2_dly2);
else
	clk2_Din <= (~sel) & (~clk1_dly2);

always @(posedge clk1 or negedge rst_n)
if(!rst_n) begin
clk1_dly1 <= 0; clk1_dly2 <= 0; end
else begin
clk1_dly1 <= clk1_Din; clk1_dly2 <= clk1_dly1; end

always @(posedge clk2 or negedge rst_n)
if(!rst_n) begin
clk2_dly1 <= 0; clk2_dly2 <= 0; end
else begin
clk2_dly1 <= clk2_Din; clk2_dly2 <= clk2_dly1; end

assign clk_out = (clk1_dly2 & clk1)|(clk2_dly2 & clk2);
endmodule