16 、FPGA之纯PL按键实验

实验基本目的:实验手册PL的流水灯,基本流程参考手册;

逻辑代码解析:

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 03/11/2020 07:37:12 PM
// Design Name: 
// Module Name: PL
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module PL(
clk,
rst_n,
sw,
led
 );
 
 input clk;
 input rst_n;
 input [3:0]sw;
 output [3:0]led;
 
 reg [3:0] sw_reg_0;
 always@(posedge clk or negedge rst_n)
 if(!rst_n)
   begin
   sw_reg_0<=4'b1111;
   end
 else
   begin
   sw_reg_0<=sw;
   end
   
    reg [3:0] sw_reg_1;
   always@(posedge clk or negedge rst_n)
   if(!rst_n)
     begin
     sw_reg_1<=4'b1111;
     end
   else
     begin
     sw_reg_1<=sw_reg_0;
     end
   
reg [19:0]cnt; 
wire [3:0]key_an_0;  
 assign key_an_0= sw_reg_0 &(~sw_reg_1);
 
always@(posedge clk or negedge rst_n)
if (!rst_n)
  begin
  end                    // 1/50MHZ=0.02us
else if(cnt==20'h186a0)  //20000us/0.02us=1000000
 begin
 cnt<=20'h00000;
 end 
 else if(key_an_0)
    begin
    cnt<=20'h00000;
    end
 else 
 begin
 cnt<=cnt+1'b1;
 end
 
 reg [3:0] sw_reg_2;
 always@(posedge clk or negedge rst_n)
 if (!rst_n)
    begin
    sw_reg_2<=4'b1111;
    end
else if(cnt==20'h186a0)
    begin
    sw_reg_2<=sw;
    end
    
    reg [3:0] sw_reg_3;
       always@(posedge clk or negedge rst_n)
       if(!rst_n)
         begin
         sw_reg_3<=4'b1111;
         end
       else
         begin
         sw_reg_3<=sw_reg_2;
         end
wire [3:0]key_an_1;   
assign key_an_1= sw_reg_3& (~sw_reg_2);

reg [3:0] led_reg;

always@(posedge clk or negedge rst_n)
if (!rst_n)
begin
led_reg<=4'b0000;
end
else
begin
if(key_an_1[0]) led_reg[0]<=~led_reg[0];
if(key_an_1[1]) led_reg[1]<=~led_reg[1];
if(key_an_1[2]) led_reg[2]<=~led_reg[2];
if(key_an_1[3]) led_reg[3]<=~led_reg[3];
end

assign led= led_reg;
endmodule

主要是按键消除抖动的时间计算

因为按键会有20~30ms的抖动时间,因此需要在抖动之后在检测,按键是否真的被按下,

因为FPGA的芯片时钟是50MHZ ,也就是脉冲每0.02us变化一次, 因为抖动时间是20~30ms,

[20ms/0.02us,30ms/0.02us]为消除抖动区间[20'h186a0,24'h16e360]

16 、FPGA之纯PL按键实验

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