18.FPGA键盘控制流水灯Modelsim仿真

1.Error (10112): Ignored design unit "key_led" at key_led.v(1) due to previous errors是指前面有编译出错的地方，解决方法：从第一个error开始排查bug
2.block中应该给reg赋值。所以output reg[3:0] led

$display("Running testbench")用于print信息

24'd1000_0000，24是10^7化成二进制之后的位数

begin里面是顺序执行的，因此如下代码，是延时200clk之后，再执行下一条延时语句

Quartus II和Modelsim联调的时候，只要在Quartus II修改激励文件，在Modelsim中reload就好。在wave窗口restart，就可以看到新的仿真波形了

	#200 key<=4'b1101;
	#400 key<=4'b1011;

流水灯代码：

module key_led(
	input		clk,
	input		rst_n,
	input [3:0]	key,
	
	output reg[3:0] led
);

reg[23:0]cnt;
reg[1:0]led_ctrl;

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		cnt<=24'd0;
	else
		if(cnt<24'd100)
			cnt<=cnt+1'b1;
		else
			if(cnt<24'd100)
				cnt<=cnt+1'b1;
			else
				cnt<=24'd0;
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		led_ctrl<=1'd0;
	else
		if(cnt<24'd25)
			led_ctrl<=2'd0;
		else if(cnt<=24'd50)
			led_ctrl<=2'd1;
		else if(cnt<=75)
			led_ctrl<=2'd2;
		else
			led_ctrl=2'd3;
			
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n)
		led<=4'b0000;
	else
		if(key[0]==1'b0)
			case(led_ctrl)
				2'd0:	led<=4'b1000;
				2'd1:	led<=4'b0100;
				2'd2:	led<=4'b0010;
				2'd3:	led<=4'b0001;
			endcase
		else if(key[1]==1'b0)
			case(led_ctrl)
				2'd0:	led<=4'b0001;
				2'd1:	led<=4'b0010;
				2'd2:	led<=4'b0100;
				2'd3:	led<=4'b1000;
			endcase
		else if(key[2]==1'b0)
			case(led_ctrl)
				2'd0:	led<=4'b1111;
				2'd1:	led<=4'b0000;
				2'd2:	led<=4'b1111;
				2'd3:	led<=4'b1000;
			endcase
		else if(key[3]==1'b0)	
			led<=4'b1111;
		else
			led<=4'b0000;
end
			
endmodule

激励文件代码：

`timescale 1 ns/ 1 ns
module key_led_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg [3:0] key;
reg rst_n;
// wires                                               
wire [3:0]  led;

// assign statements (if any)                          
key_led i1 (
// port map - connection between master ports and signals/registers   
	.clk(clk),
	.key(key),
	.led(led),
	.rst_n(rst_n)
);
initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin                          
	clk=1'b0;
	rst_n=1'b1;
	key<=4'b1110;
	#200 key<=4'b1101;
	#400 key<=4'b1011;
	#600 key<=4'b0111;
	#800 $stop;
// --> end                                             
$display("Running testbench");                       
end                                                    
always#1 clk=~clk;
/*always@(posedge clk)begin
	if(cnt==0)
		key<=4'b1110;
	else if(cnt==50)
		key<=4'b1101;
	else if(cnt==100)
		key<=4'b1011;
	else if(cnt==150)
		key<=4'b0111;
	
end*/                                                                                          
// --> end                                                                                                 
endmodule

效果如下：

quartus II中，tools→Netlist→RTL Viewer可以看到生成的门电路图