[INTEL (ALTERA)] CSR related issues of R-Tile IP of quartus design example using Compute Express Link (CXL)

illustrate

Due to an issue with Intel® Quartus® Prime Professional Edition software 23.2 and later, the CSR access data width in the Intel® FPGA IP for Compute Express Link* (CXL*) Type2/3 Design Example R-Tile was changed from 32 bits to 64 bit; this can result in a mismatch between software driver functionality and user CSR logic design.

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Solution

This issue is not planned to be fixed in a future release of Intel® Quartus® Prime Edition software.

To work around this issue,  see  the offending code  example:

1. 打开 / hardware_test_design/common/ex_default_csr/ex_default_csr_avmm_slave.sv

2.  Implement CSR using  64-bit data width instead of the standard 32-bit data width   .

64-bit data width
always @(posedge clk)
if (!reset_n) start
ats_stu <= 5'b0;
ats_en <= 1'b0;
ptm_eg <= 8'b0;
ptm_rs <= 1'b0;
ptm_en <= 1'b0 ;
end else if (write &config_access) start
case(address[20:0])
21'h00E00: start
ats_stu <= write data[60:56];
ats_en <= write data[63];
end
21'h00E18 : start
ptm_eg <= write data[15:8];
ptm_rs <= write data[1];
ptm_en <= write data[0];
end
default; end
end

read logic
always @(posedge clk)
if (!reset_n) begin
cfg_readdata <= 64'h0;
end else if (read&&config_access) begin
case(address[20:0])
21'h00E00: cfg_readdata <= { {ats_en, 10 'b0,ats_stu,16'h0020},EX_CAP_HEADER_ATS};
21'h00E04: cfg_readdata <= { {ats_en, 10'b0,ats_stu,16'h0020},32'b0};
21'h00E10: cfg_readdata <= {EX_CAP_HEADER_PTM_CAP, EX_CAP_HEADER_PTM};
21'h00E14: cfg_readdata <= {EX_CAP_HEADER_PTM_CAP, 32'b0};
21'h00E18: cfg_readdata <= {32'b0, {16'h0, ptm_eg, 6'h0, 1'b0, ptm_en}};
Default Values: cfg_readdata <= {32'b0, 32'hffff_ffff};
end
else start
cfg_readdata <= 64'h0;
end