A memory barrier is a general term used to refer to one or more instructions that enforce a synchronization event on the processor when executing a load ( load) or store ( ) instruction. storeBoth the ARMv7-M and ARMv6-M architectures provide three memory barrier instructions to support the memory order model. The three memory barrier instructions are: DMB, DSBand ISB.
Article directory
1 Overview of DMB, DSB and ISB
(1) Data Memory Barrier (DMB): Data memory barrier
is mainly used in multi-core processor systems, and different processors may execute data memory transfer instructions at the same time. DMBThe instruction ensures that DMBall previous explicit data memory transfer instructions have been read or written in memory, and at the same time ensures that any subsequent data memory transfer instructions will be DMBexecuted after execution, otherwise some data transfer instructions may be executed early .
(2) Data Synchronization Barrier (DSB): Data Synchronization Barrier
In the computer architecture, the processor usually uses the instruction pipeline to improve performance when executing instructions. However, some problems will also arise. For example, in multi-threaded programming, two threads simultaneously perform read and write operations on the shared memory. Due to the reordering of read/write operations, data inconsistency will result.
When an instruction is executed DSB, it ensures that DSBall previous explicit data-memory transfer instructions have completed reading or writing in memory, while ensuring that any subsequent instruction will DSBstart executing after that.
(3) Instruction Synchronization Barrier (ISB): The pipeline of the instruction synchronization barrier instruction allows the processor to execute different stages of multiple instructions at the same time. However, such parallel execution may cause some problems, especially when context switching is involved, such as real-time operation System task switching. When the context is switched, the instructions in the instruction pipeline may still be executed, but the context has changed at this time, resulting in incorrect instruction execution results.
By inserting ISBinstructions, the processor will flush all the instructions in the pipeline, thus ensuring that previous instructions will not affect the execution of subsequent instructions, and subsequent instructions will be re-fetched from the correct context.
Tips: Most CPU architectures have ISB semantics (automatic execution) at the entry and exit of exceptions.
When the processor executes code, it may encounter abnormal conditions, such as interrupts, system calls, or other external event triggers. In these cases, the processor needs to temporarily suspend the current task, turn to handle the exception, and then return to the previous task to continue execution.
Specifically, the processor performs an ISB operation before making an exception entry. The purpose of doing this is to refresh the instruction pipeline, to ensure that the instructions of the exception handler are executed from the correct address, and to prevent the instructions before the exception from interfering with the exception handler.
After the execution of the exception handler is completed, the processor needs to return to the previously interrupted task to continue execution. The processor also performs ISB operations before returning from an exception. The purpose of this is to refresh the instruction pipeline, to ensure that the instruction is re-acquired from the correct address when returning, and to prevent the instruction of the exception handler from interfering with the normal task.
(4) API
In C language, you can use functions provided by CMSIS or various C compilers to call memory barrier instructions.
| memory barrier | CMSIS function | Integrated C compiler in MDK-ARM, DS-5 and RVDS |
|---|---|---|
| DMB | _DMB() | _dmb(0xF) |
| DSB | _DSB() | _dsb(0xF) |
| ISB | _ISB() | _isb(0xF) |
- The representation here
0xFspecifies a complete system barrier (Full System Barrier) operation, which will ensure the barrier operation of reading and writing, and is applicable to the internal memory of the chip (such as SRAM) and external memory (such as the HyperRAM connected by itself), no matter whether the memory is Shareable or Non -Shareable.
2 Typical cases of three types of instructions
1. The DMB
DMB instruction ensures that two memory accesses are executed in the correct order. In fact, DMBit is not used much in Cortex-M processors, because Cortex-M processors do not reorder memory transactions ( Memory transaction). DMBBut it is necessary if you want the software to be reusable on other ARM processors (such as Cortex-M ported to Cortex-A), especially in multi-master systems . Here are a few examples:
(1)
When DMA uses the DMA controller, DMBa barrier needs to be inserted between the CPU memory access and the DMA operation to ensure that the current memory read and write operations of the CPU are completed before the DMA starts.
(2) Semaphores in multi-core systems
In multi-core systems, semaphores are used for inter-core synchronization. Required DMBto enforce the specified memory execution order to avoid potential race conditions or data inconsistencies.
Before a core accesses a shared resource, it checks the state of the semaphore. If the semaphore has already been acquired by another core, the current core must wait until the semaphore state becomes available. This waiting process needs to ensure that after one core releases the semaphore, other cores can immediately see the change of the semaphore state, instead of causing errors due to processor optimization or invalid reads caused by caches.
Here, the role of DMB is to enforce memory order. By inserting a DMB barrier before the core acquires the semaphore, it is ensured that all memory operations complete before the DMB. In this way, after one core releases the semaphore, the operation of other cores to acquire the semaphore can see the latest semaphore state, so as to achieve correct synchronization.
(3) Mailboxes in multi-core systems
Similarly, when communicating through the mailbox mechanism between cores, it is necessary to use DMBthe correct sequence of memory accesses to the mailboxes to avoid communication problems.
2.
In the Cortex-M processor, the DSB DSBcan be used to:
(1) Ensure that the modification to SCS( System Control Space) takes effect before the execution of the next instruction
In the ARM Cortex-M processor, SCSit is a special memory area that contains some system control registers and configuration information for managing various functions and features of the processor and system. Registers accessed SCScan affect the behavior of the processor, such as enabling or disabling specific interrupts, configuring clocks, setting system control bits, etc. In order to ensure that SCSthe modification to takes effect before the execution of the next instruction, it is necessary to use DSBinstructions for data synchronization.
(2) Ensure that the data in the memory has been updated before executing privileged instructions
In the ARM Cortex-M processor, some special instructions such as SVC( Supervisor Call, privileged call), WFI( Wait For Interrupt, wait for interrupt), WFE( Wait For Event, wait for event) Operations that involve switching privilege levels or waiting for system events to occur require the use of DSBinstructions.
3. The ISB
ISB instruction is used to clear the pipeline to ensure that ISBthe effects of all context modification operations before the instruction are correctly recognized by subsequent operations. There is a very typical example:
Modification of the CONTROL register
After modifying CONTROLthe register, ISBthe instruction should be used. For example, we modify CONTROLthe relevant fields in the register to enter the privileged mode, and then the next line of code is some privileged operations. Before that, we need to use ISBinstructions to let the processor correctly identify the new privileged level.
3 summary
This article explains in detail the meaning and timing of the three instructions DMB, DSB and ISB. But most simple processors do not reorder memory transfers, so the requirements of the architecture and the implementation of the processor are different. For example, most applications will run correctly on existing Cortex-M processors without using any memory barrier instructions.
However, if the application is being ported to a high-end processor, the omission of the memory barrier instruction may cause the application to malfunction. The use of memory barriers is also important if the software is to be ported to a system with multiple processors. For example, when dealing with semaphores in a multiprocessor system, memory barrier instructions should be used to ensure that other processors in the system can observe data changes in the correct order.
ARM recommends that software developers develop software based on architectural requirements rather than processor-specific behavior. This ensures portability and reusability of software code. Processor-specific behavior may also vary between releases of the same architecture.